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net: phy: DP83TC811: Introduce support for the DP83TC811 phy
Add support for the DP83811 phy. The DP83811 supports both rgmii and sgmii interfaces. There are 2 part numbers for this the DP83TC811R does not reliably support the SGMII interface but the DP83TC811S will. There is not a way to differentiate these parts from the hardware or register set. So this is controlled via the DT to indicate which phy mode is required. Or the part can be strapped to a certain interface. Data sheet can be found here: http://www.ti.com/product/DP83TC811S-Q1/description http://www.ti.com/product/DP83TC811R-Q1/description Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dan Murphy
David S. Miller
parent
443e2dab32
commit
b753a9faaf
@ -291,6 +291,11 @@ config DP83822_PHY
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---help---
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Supports the DP83822 PHY.
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config DP83TC811_PHY
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tristate "Texas Instruments DP83TC822 PHY"
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---help---
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Supports the DP83TC822 PHY.
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config DP83848_PHY
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tristate "Texas Instruments DP83848 PHY"
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---help---
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@ -58,6 +58,7 @@ obj-$(CONFIG_CORTINA_PHY) += cortina.o
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obj-$(CONFIG_DAVICOM_PHY) += davicom.o
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obj-$(CONFIG_DP83640_PHY) += dp83640.o
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obj-$(CONFIG_DP83822_PHY) += dp83822.o
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obj-$(CONFIG_DP83TC811_PHY) += dp83tc811.o
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obj-$(CONFIG_DP83848_PHY) += dp83848.o
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obj-$(CONFIG_DP83867_PHY) += dp83867.o
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obj-$(CONFIG_FIXED_PHY) += fixed_phy.o
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347
drivers/net/phy/dp83tc811.c
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347
drivers/net/phy/dp83tc811.c
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@ -0,0 +1,347 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for the Texas Instruments DP83TC811 PHY
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*
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*/
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#include <linux/ethtool.h>
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#include <linux/etherdevice.h>
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#include <linux/kernel.h>
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#include <linux/mii.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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#define DP83TC811_PHY_ID 0x2000a253
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#define DP83811_DEVADDR 0x1f
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#define MII_DP83811_SGMII_CTRL 0x09
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#define MII_DP83811_INT_STAT1 0x12
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#define MII_DP83811_INT_STAT2 0x13
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#define MII_DP83811_RESET_CTRL 0x1f
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#define DP83811_HW_RESET BIT(15)
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#define DP83811_SW_RESET BIT(14)
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/* INT_STAT1 bits */
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#define DP83811_RX_ERR_HF_INT_EN BIT(0)
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#define DP83811_MS_TRAINING_INT_EN BIT(1)
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#define DP83811_ANEG_COMPLETE_INT_EN BIT(2)
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#define DP83811_ESD_EVENT_INT_EN BIT(3)
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#define DP83811_WOL_INT_EN BIT(4)
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#define DP83811_LINK_STAT_INT_EN BIT(5)
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#define DP83811_ENERGY_DET_INT_EN BIT(6)
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#define DP83811_LINK_QUAL_INT_EN BIT(7)
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/* INT_STAT2 bits */
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#define DP83811_JABBER_DET_INT_EN BIT(0)
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#define DP83811_POLARITY_INT_EN BIT(1)
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#define DP83811_SLEEP_MODE_INT_EN BIT(2)
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#define DP83811_OVERTEMP_INT_EN BIT(3)
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#define DP83811_OVERVOLTAGE_INT_EN BIT(6)
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#define DP83811_UNDERVOLTAGE_INT_EN BIT(7)
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#define MII_DP83811_RXSOP1 0x04a5
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#define MII_DP83811_RXSOP2 0x04a6
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#define MII_DP83811_RXSOP3 0x04a7
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/* WoL Registers */
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#define MII_DP83811_WOL_CFG 0x04a0
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#define MII_DP83811_WOL_STAT 0x04a1
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#define MII_DP83811_WOL_DA1 0x04a2
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#define MII_DP83811_WOL_DA2 0x04a3
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#define MII_DP83811_WOL_DA3 0x04a4
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/* WoL bits */
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#define DP83811_WOL_MAGIC_EN BIT(0)
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#define DP83811_WOL_SECURE_ON BIT(5)
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#define DP83811_WOL_EN BIT(7)
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#define DP83811_WOL_INDICATION_SEL BIT(8)
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#define DP83811_WOL_CLR_INDICATION BIT(11)
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/* SGMII CTRL bits */
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#define DP83811_TDR_AUTO BIT(8)
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#define DP83811_SGMII_EN BIT(12)
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#define DP83811_SGMII_AUTO_NEG_EN BIT(13)
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#define DP83811_SGMII_TX_ERR_DIS BIT(14)
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#define DP83811_SGMII_SOFT_RESET BIT(15)
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static int dp83811_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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err = phy_read(phydev, MII_DP83811_INT_STAT1);
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if (err < 0)
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return err;
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err = phy_read(phydev, MII_DP83811_INT_STAT2);
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if (err < 0)
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return err;
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return 0;
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}
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static int dp83811_set_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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struct net_device *ndev = phydev->attached_dev;
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const u8 *mac;
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u16 value;
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if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
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mac = (const u8 *)ndev->dev_addr;
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if (!is_valid_ether_addr(mac))
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return -EINVAL;
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/* MAC addresses start with byte 5, but stored in mac[0].
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* 811 PHYs store bytes 4|5, 2|3, 0|1
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*/
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phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA1,
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(mac[1] << 8) | mac[0]);
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phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA2,
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(mac[3] << 8) | mac[2]);
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phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA3,
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(mac[5] << 8) | mac[4]);
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value = phy_read_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_WOL_CFG);
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if (wol->wolopts & WAKE_MAGIC)
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value |= DP83811_WOL_MAGIC_EN;
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else
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value &= ~DP83811_WOL_MAGIC_EN;
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if (wol->wolopts & WAKE_MAGICSECURE) {
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phy_write_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_RXSOP1,
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(wol->sopass[1] << 8) | wol->sopass[0]);
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phy_write_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_RXSOP2,
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(wol->sopass[3] << 8) | wol->sopass[2]);
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phy_write_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_RXSOP3,
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(wol->sopass[5] << 8) | wol->sopass[4]);
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value |= DP83811_WOL_SECURE_ON;
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} else {
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value &= ~DP83811_WOL_SECURE_ON;
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}
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value |= (DP83811_WOL_EN | DP83811_WOL_INDICATION_SEL |
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DP83811_WOL_CLR_INDICATION);
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phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
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value);
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} else {
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value = phy_read_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_WOL_CFG);
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value &= ~DP83811_WOL_EN;
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phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
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value);
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}
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return 0;
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}
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static void dp83811_get_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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u16 sopass_val;
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int value;
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wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
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wol->wolopts = 0;
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value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
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if (value & DP83811_WOL_MAGIC_EN)
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wol->wolopts |= WAKE_MAGIC;
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if (value & DP83811_WOL_SECURE_ON) {
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sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_RXSOP1);
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wol->sopass[0] = (sopass_val & 0xff);
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wol->sopass[1] = (sopass_val >> 8);
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sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_RXSOP2);
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wol->sopass[2] = (sopass_val & 0xff);
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wol->sopass[3] = (sopass_val >> 8);
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sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_RXSOP3);
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wol->sopass[4] = (sopass_val & 0xff);
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wol->sopass[5] = (sopass_val >> 8);
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wol->wolopts |= WAKE_MAGICSECURE;
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}
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/* WoL is not enabled so set wolopts to 0 */
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if (!(value & DP83811_WOL_EN))
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wol->wolopts = 0;
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}
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static int dp83811_config_intr(struct phy_device *phydev)
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{
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int misr_status, err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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misr_status = phy_read(phydev, MII_DP83811_INT_STAT1);
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if (misr_status < 0)
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return misr_status;
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misr_status |= (DP83811_RX_ERR_HF_INT_EN |
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DP83811_MS_TRAINING_INT_EN |
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DP83811_ANEG_COMPLETE_INT_EN |
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DP83811_ESD_EVENT_INT_EN |
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DP83811_WOL_INT_EN |
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DP83811_LINK_STAT_INT_EN |
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DP83811_ENERGY_DET_INT_EN |
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DP83811_LINK_QUAL_INT_EN);
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err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status);
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if (err < 0)
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return err;
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misr_status = phy_read(phydev, MII_DP83811_INT_STAT2);
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if (misr_status < 0)
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return misr_status;
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misr_status |= (DP83811_JABBER_DET_INT_EN |
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DP83811_POLARITY_INT_EN |
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DP83811_SLEEP_MODE_INT_EN |
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DP83811_OVERTEMP_INT_EN |
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DP83811_OVERVOLTAGE_INT_EN |
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DP83811_UNDERVOLTAGE_INT_EN);
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err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status);
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} else {
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err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
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if (err < 0)
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return err;
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err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
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}
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return err;
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}
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static int dp83811_config_aneg(struct phy_device *phydev)
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{
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int value, err;
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if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
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value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
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if (phydev->autoneg == AUTONEG_ENABLE) {
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err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
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(DP83811_SGMII_AUTO_NEG_EN | value));
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if (err < 0)
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return err;
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} else {
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err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
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(~DP83811_SGMII_AUTO_NEG_EN & value));
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if (err < 0)
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return err;
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}
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}
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return genphy_config_aneg(phydev);
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}
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static int dp83811_config_init(struct phy_device *phydev)
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{
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int value, err;
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err = genphy_config_init(phydev);
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if (err < 0)
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return err;
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if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
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value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
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if (!(value & DP83811_SGMII_EN)) {
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err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
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(DP83811_SGMII_EN | value));
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if (err < 0)
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return err;
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} else {
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err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
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(~DP83811_SGMII_EN & value));
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if (err < 0)
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return err;
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}
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}
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value = DP83811_WOL_MAGIC_EN | DP83811_WOL_SECURE_ON | DP83811_WOL_EN;
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return phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
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value);
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}
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static int dp83811_phy_reset(struct phy_device *phydev)
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{
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int err;
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err = phy_write(phydev, MII_DP83811_RESET_CTRL, DP83811_HW_RESET);
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if (err < 0)
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return err;
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return 0;
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}
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static int dp83811_suspend(struct phy_device *phydev)
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{
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int value;
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value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
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if (!(value & DP83811_WOL_EN))
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genphy_suspend(phydev);
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return 0;
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}
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static int dp83811_resume(struct phy_device *phydev)
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{
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int value;
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genphy_resume(phydev);
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value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
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phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, value |
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DP83811_WOL_CLR_INDICATION);
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return 0;
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}
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static struct phy_driver dp83811_driver[] = {
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{
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.phy_id = DP83TC811_PHY_ID,
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.phy_id_mask = 0xfffffff0,
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.name = "TI DP83TC811",
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.features = PHY_BASIC_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.config_init = dp83811_config_init,
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.config_aneg = dp83811_config_aneg,
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.soft_reset = dp83811_phy_reset,
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.get_wol = dp83811_get_wol,
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.set_wol = dp83811_set_wol,
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.ack_interrupt = dp83811_ack_interrupt,
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.config_intr = dp83811_config_intr,
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.suspend = dp83811_suspend,
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.resume = dp83811_resume,
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},
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};
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module_phy_driver(dp83811_driver);
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static struct mdio_device_id __maybe_unused dp83811_tbl[] = {
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{ DP83TC811_PHY_ID, 0xfffffff0 },
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{ },
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};
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MODULE_DEVICE_TABLE(mdio, dp83811_tbl);
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MODULE_DESCRIPTION("Texas Instruments DP83TC811 PHY driver");
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MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
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MODULE_LICENSE("GPL");
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