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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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amd64_edac: remove memory and GART TLB error decoders
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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5110dbdeab
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@ -2209,28 +2209,6 @@ static int amd64_get_error_info(struct mem_ctl_info *mci,
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return 1;
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}
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static inline void amd64_decode_gart_tlb_error(struct mem_ctl_info *mci,
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struct err_regs *info)
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{
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u32 ec = ERROR_CODE(info->nbsl);
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amd64_mc_printk(mci, KERN_ERR,
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"GART TLB event: transaction type(%s), "
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"cache level(%s)\n", TT_MSG(ec), LL_MSG(ec));
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}
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static inline void amd64_decode_mem_cache_error(struct mem_ctl_info *mci,
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struct err_regs *info)
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{
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u32 ec = ERROR_CODE(info->nbsl);
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amd64_mc_printk(mci, KERN_ERR,
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"cache hierarchy error: memory transaction type(%s), "
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"transaction type(%s), cache level(%s)\n",
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RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
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}
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/*
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* Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR
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* ADDRESS and process.
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@ -2411,19 +2389,19 @@ void amd64_decode_nb_mce(struct mem_ctl_info *mci, struct err_regs *regs,
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if (!report_gart_errors)
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return;
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pr_emerg("GART TLB error\n");
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amd64_decode_gart_tlb_error(mci, regs);
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pr_emerg(" GART TLB error, Transaction: %s, Cache Level %s\n",
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TT_MSG(ec), LL_MSG(ec));
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} else if (MEM_ERROR(ec)) {
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pr_emerg("Memory/Cache error\n");
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amd64_decode_mem_cache_error(mci, regs);
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pr_emerg(" Memory/Cache error, Transaction: %s, Type: %s,"
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" Cache Level: %s",
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RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
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} else if (BUS_ERROR(ec)) {
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pr_emerg("Bus (Link/DRAM) error\n");
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pr_emerg(" Bus (Link/DRAM) error\n");
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amd64_decode_bus_error(mci, regs);
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} else {
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/* shouldn't reach here! */
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amd64_mc_printk(mci, KERN_WARNING,
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"%s(): unknown MCE error 0x%x\n", __func__,
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ec);
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"%s(): unknown MCE error 0x%x\n", __func__, ec);
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}
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pr_emerg("%s.\n", EXT_ERR_MSG(xec));
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