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drm/i915: set AUD_CONFIG N_value_index for DisplayPort

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It should be programmed to "0" for HDMI or "1" for DisplayPort.

This enables DisplayPort audio for

- HP EliteBook 8460p
  (whose BIOS does not set the N_value_index bit for us)

- DisplayPort monitor hot plugged after boot
  (otherwise most BIOS will fill the N_value_index bit for us)

Tested-by: Robert Lemaire <rlemaire@suse.com>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Wu Fengguang <fengguang.wu@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Wu Fengguang 2012-01-06 14:41:31 -06:00 committed by Daniel Vetter
parent 6dc0e816bb
commit b6daa025b1
2 changed files with 19 additions and 1 deletions
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12
drivers/gpu/drm/i915/i915_reg.h
View File

@ -3742,4 +3742,16 @@
*/ */
#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
#define IBX_AUD_CONFIG_A 0xe2000
#define CPT_AUD_CONFIG_A 0xe5000
#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
#define AUD_CONFIG_UPPER_N_SHIFT 20
#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
#define AUD_CONFIG_LOWER_N_SHIFT 4
#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
#endif /* _I915_REG_H_ */ #endif /* _I915_REG_H_ */

8
drivers/gpu/drm/i915/intel_display.c
View File

@ -6141,15 +6141,18 @@ static void ironlake_write_eld(struct drm_connector *connector,
uint32_t i; uint32_t i;
int len; int len;
int hdmiw_hdmiedid; int hdmiw_hdmiedid;
int aud_config;
int aud_cntl_st; int aud_cntl_st;
int aud_cntrl_st2; int aud_cntrl_st2;
if (HAS_PCH_IBX(connector->dev)) { if (HAS_PCH_IBX(connector->dev)) {
hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A; hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
aud_config = IBX_AUD_CONFIG_A;
aud_cntl_st = IBX_AUD_CNTL_ST_A; aud_cntl_st = IBX_AUD_CNTL_ST_A;
aud_cntrl_st2 = IBX_AUD_CNTL_ST2; aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
} else { } else {
hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A; hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
aud_config = CPT_AUD_CONFIG_A;
aud_cntl_st = CPT_AUD_CNTL_ST_A; aud_cntl_st = CPT_AUD_CNTL_ST_A;
aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
} }
@ -6157,6 +6160,7 @@ static void ironlake_write_eld(struct drm_connector *connector,
i = to_intel_crtc(crtc)->pipe; i = to_intel_crtc(crtc)->pipe;
hdmiw_hdmiedid += i * 0x100; hdmiw_hdmiedid += i * 0x100;
aud_cntl_st += i * 0x100; aud_cntl_st += i * 0x100;
aud_config += i * 0x100;
DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i)); DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
@ -6176,7 +6180,9 @@ static void ironlake_write_eld(struct drm_connector *connector,
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
} I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
} else
I915_WRITE(aud_config, 0);
if (intel_eld_uptodate(connector, if (intel_eld_uptodate(connector,
aud_cntrl_st2, eldv, aud_cntrl_st2, eldv,