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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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gpio: tegra186: Add support for pin ranges
Add support for Tegra SoC generations to specify a list of pin ranges that map GPIOs to ranges of pins in the pin controller. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-3-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -58,11 +58,20 @@ struct tegra_gpio_port {
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unsigned int pins;
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};
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struct tegra186_pin_range {
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unsigned int offset;
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const char *group;
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};
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struct tegra_gpio_soc {
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const struct tegra_gpio_port *ports;
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unsigned int num_ports;
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const char *name;
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unsigned int instance;
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const struct tegra186_pin_range *pin_ranges;
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unsigned int num_pin_ranges;
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const char *pinmux;
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};
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struct tegra_gpio {
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@ -254,6 +263,50 @@ static int tegra186_gpio_set_config(struct gpio_chip *chip,
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return 0;
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}
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static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
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{
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struct tegra_gpio *gpio = gpiochip_get_data(chip);
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struct pinctrl_dev *pctldev;
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struct device_node *np;
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unsigned int i, j;
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int err;
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if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
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return 0;
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np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
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if (!np)
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return -ENODEV;
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pctldev = of_pinctrl_get(np);
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of_node_put(np);
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if (!pctldev)
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return -EPROBE_DEFER;
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for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
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unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
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const char *group = gpio->soc->pin_ranges[i].group;
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port = pin / 8;
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pin = pin % 8;
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if (port >= gpio->soc->num_ports) {
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dev_warn(chip->parent, "invalid port %u for %s\n",
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port, group);
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continue;
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}
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for (j = 0; j < port; j++)
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pin += gpio->soc->ports[j].pins;
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err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
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if (err < 0)
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return err;
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}
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return 0;
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}
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static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
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const struct of_phandle_args *spec,
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u32 *flags)
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@ -578,12 +631,15 @@ static int tegra186_gpio_probe(struct platform_device *pdev)
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gpio->gpio.label = gpio->soc->name;
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gpio->gpio.parent = &pdev->dev;
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gpio->gpio.request = gpiochip_generic_request;
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gpio->gpio.free = gpiochip_generic_free;
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gpio->gpio.get_direction = tegra186_gpio_get_direction;
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gpio->gpio.direction_input = tegra186_gpio_direction_input;
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gpio->gpio.direction_output = tegra186_gpio_direction_output;
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gpio->gpio.get = tegra186_gpio_get,
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gpio->gpio.set = tegra186_gpio_set;
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gpio->gpio.set_config = tegra186_gpio_set_config;
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gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
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gpio->gpio.base = -1;
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