mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Rebase of Emilio's clk-sunxi-for-3.16 on top of clk-next
Fixed a few compilation warnings exposed by a patch introduced during the 3.16 merge window. Original tag message: Allwinner sunXi SoCs clock changes This pull contains some new code to add support for A31 clocks by Maxime and Boris. It also reworks the driver a bit to avoid having a huge single file when we have a full folder for ourselves, and separating different functional units makes sense. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJTmBUrAAoJEBx+YmzsjxAgxE4P/3YdHQNnRmLEnBuW+RivwTzj abwwYqnWXBcmr2XA7jzbCVQlTrLLoodcq00gcN/O78UvFL34kPv69WDjsmz9cdG5 bUV+97b7D7RRAbzWurHEZOgFabZGX6kw1MwPbh6inikakvwxzm+r/2oKDAnpjzfp QVWdcgrL6sBe722QJrkDOiLGOchRpJctWpH++bBow3hIzxEYSt5xpNNCgEXrRqql AMurwCTL/2UfJmuuMVxNdXBkju2/hHMuZipD6ehMt34JZhiMsXT+u7AnYSfvHuO8 KLIlCIHSi7olhg+I+9IuWf62uNt1FjjO/kDKdya+bJCfuaBeT8XUCuAhbYZVw0xX b1my9boUlUXtU5CLmBHWJU0EOaZczDQckxO28UoBwIuSvRgtzUBobRZI4rMJ7Xad dAqaTsQ00VOgVaahPawdSYIURMRXKXJgvqhGMU9jXjOuZFqa0hoRlD9IEUOUBa/G vlKgyC4jXI6+yE33yQuD4Se/eRpXwloPgHotHlW8G7HnDmarCnNbr0+YK8VSvgjT FPS4YC+j/peSGgnmObw4XfngUUFMPQP/jVKY8ubwFr8QB6F8lGXFyVA1Ppr8QCJB mW/e59cH+McqFJwr2h1CvCVb311jjQoLgmyRmXbXXrWF7xafRykN8lkNdeYs0ToM 0d9V7sEKYpqUzd06lpL3 =RmPH -----END PGP SIGNATURE----- Merge tag 'sunxi-clk-for-3.16-2' of https://github.com/mripard/linux into clk-next Rebase of Emilio's clk-sunxi-for-3.16 on top of clk-next Fixed a few compilation warnings exposed by a patch introduced during the 3.16 merge window. Original tag message: Allwinner sunXi SoCs clock changes This pull contains some new code to add support for A31 clocks by Maxime and Boris. It also reworks the driver a bit to avoid having a huge single file when we have a full folder for ourselves, and separating different functional units makes sense.
This commit is contained in:
Mike Turquette
commit
b640a6037c
@ -20,12 +20,15 @@ Required properties:
|
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"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
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"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
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"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
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"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
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"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
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"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
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"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
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"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
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"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
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"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
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"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
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"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
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"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
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"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
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"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
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@ -41,6 +44,7 @@ Required properties:
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"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
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"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
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"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
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"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
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Required properties for all clocks:
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- reg : shall be the control register address for the clock.
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@ -3,3 +3,7 @@
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#
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obj-y += clk-sunxi.o clk-factors.o
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obj-y += clk-a10-hosc.o
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obj-y += clk-a20-gmac.o
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obj-$(CONFIG_MFD_SUN6I_PRCM) += clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o
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73
drivers/clk/sunxi/clk-a10-hosc.c
Normal file
73
drivers/clk/sunxi/clk-a10-hosc.c
Normal file
@ -0,0 +1,73 @@
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/*
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* Copyright 2013 Emilio López
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*
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* Emilio López <emilio@elopez.com.ar>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#define SUNXI_OSC24M_GATE 0
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static DEFINE_SPINLOCK(hosc_lock);
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static void __init sun4i_osc_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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struct clk_fixed_rate *fixed;
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struct clk_gate *gate;
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const char *clk_name = node->name;
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u32 rate;
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if (of_property_read_u32(node, "clock-frequency", &rate))
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return;
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/* allocate fixed-rate and gate clock structs */
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fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
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if (!fixed)
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return;
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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if (!gate)
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goto err_free_fixed;
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of_property_read_string(node, "clock-output-names", &clk_name);
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/* set up gate and fixed rate properties */
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gate->reg = of_iomap(node, 0);
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gate->bit_idx = SUNXI_OSC24M_GATE;
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gate->lock = &hosc_lock;
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fixed->fixed_rate = rate;
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clk = clk_register_composite(NULL, clk_name,
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NULL, 0,
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NULL, NULL,
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&fixed->hw, &clk_fixed_rate_ops,
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&gate->hw, &clk_gate_ops,
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CLK_IS_ROOT);
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if (IS_ERR(clk))
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goto err_free_gate;
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, clk_name, NULL);
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return;
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err_free_gate:
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kfree(gate);
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err_free_fixed:
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kfree(fixed);
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}
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CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-a10-osc-clk", sun4i_osc_clk_setup);
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119
drivers/clk/sunxi/clk-a20-gmac.c
Normal file
119
drivers/clk/sunxi/clk-a20-gmac.c
Normal file
@ -0,0 +1,119 @@
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/*
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* Copyright 2013 Emilio López
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* Emilio López <emilio@elopez.com.ar>
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*
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* Copyright 2013 Chen-Yu Tsai
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* Chen-Yu Tsai <wens@csie.org>
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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static DEFINE_SPINLOCK(gmac_lock);
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/**
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* sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
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*
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* This clock looks something like this
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* ________________________
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* MII TX clock from PHY >-----|___________ _________|----> to GMAC core
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* GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
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* Ext. 125MHz RGMII TX clk >--|__divider__/ |
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* |________________________|
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*
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* The external 125 MHz reference is optional, i.e. GMAC can use its
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* internal TX clock just fine. The A31 GMAC clock module does not have
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* the divider controls for the external reference.
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*
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* To keep it simple, let the GMAC use either the MII TX clock for MII mode,
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* and its internal TX clock for GMII and RGMII modes. The GMAC driver should
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* select the appropriate source and gate/ungate the output to the PHY.
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*
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* Only the GMAC should use this clock. Altering the clock so that it doesn't
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* match the GMAC's operation parameters will result in the GMAC not being
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* able to send traffic out. The GMAC driver should set the clock rate and
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* enable/disable this clock to configure the required state. The clock
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* driver then responds by auto-reparenting the clock.
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*/
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#define SUN7I_A20_GMAC_GPIT 2
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#define SUN7I_A20_GMAC_MASK 0x3
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#define SUN7I_A20_GMAC_PARENTS 2
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static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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struct clk_mux *mux;
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struct clk_gate *gate;
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const char *clk_name = node->name;
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const char *parents[SUN7I_A20_GMAC_PARENTS];
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void *reg;
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if (of_property_read_string(node, "clock-output-names", &clk_name))
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return;
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/* allocate mux and gate clock structs */
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mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
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if (!mux)
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return;
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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if (!gate)
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goto free_mux;
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/* gmac clock requires exactly 2 parents */
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parents[0] = of_clk_get_parent_name(node, 0);
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parents[1] = of_clk_get_parent_name(node, 1);
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if (!parents[0] || !parents[1])
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goto free_gate;
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reg = of_iomap(node, 0);
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if (!reg)
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goto free_gate;
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/* set up gate and fixed rate properties */
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gate->reg = reg;
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gate->bit_idx = SUN7I_A20_GMAC_GPIT;
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gate->lock = &gmac_lock;
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mux->reg = reg;
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mux->mask = SUN7I_A20_GMAC_MASK;
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mux->flags = CLK_MUX_INDEX_BIT;
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mux->lock = &gmac_lock;
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clk = clk_register_composite(NULL, clk_name,
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parents, SUN7I_A20_GMAC_PARENTS,
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&mux->hw, &clk_mux_ops,
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NULL, NULL,
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&gate->hw, &clk_gate_ops,
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0);
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if (IS_ERR(clk))
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goto iounmap_reg;
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, clk_name, NULL);
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return;
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iounmap_reg:
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iounmap(reg);
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free_gate:
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kfree(gate);
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free_mux:
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kfree(mux);
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}
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CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
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sun7i_a20_gmac_clk_setup);
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99
drivers/clk/sunxi/clk-sun6i-apb0-gates.c
Normal file
99
drivers/clk/sunxi/clk-sun6i-apb0-gates.c
Normal file
@ -0,0 +1,99 @@
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/*
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* Copyright (C) 2014 Free Electrons
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*
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* License Terms: GNU General Public License v2
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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* Allwinner A31 APB0 clock gates driver
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#define SUN6I_APB0_GATES_MAX_SIZE 32
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static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct clk_onecell_data *clk_data;
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const char *clk_parent;
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const char *clk_name;
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struct resource *r;
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void __iomem *reg;
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int gate_id;
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int ngates;
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int i;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(&pdev->dev, r);
|
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if (!reg)
|
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return PTR_ERR(reg);
|
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|
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clk_parent = of_clk_get_parent_name(np, 0);
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if (!clk_parent)
|
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return -EINVAL;
|
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|
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ngates = of_property_count_strings(np, "clock-output-names");
|
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if (ngates < 0)
|
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return ngates;
|
||||
|
||||
if (!ngates || ngates > SUN6I_APB0_GATES_MAX_SIZE)
|
||||
return -EINVAL;
|
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|
||||
clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data),
|
||||
GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
clk_data->clks = devm_kzalloc(&pdev->dev,
|
||||
SUN6I_APB0_GATES_MAX_SIZE *
|
||||
sizeof(struct clk *),
|
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GFP_KERNEL);
|
||||
if (!clk_data->clks)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < ngates; i++) {
|
||||
of_property_read_string_index(np, "clock-output-names",
|
||||
i, &clk_name);
|
||||
|
||||
gate_id = i;
|
||||
of_property_read_u32_index(np, "clock-indices", i, &gate_id);
|
||||
|
||||
WARN_ON(gate_id >= SUN6I_APB0_GATES_MAX_SIZE);
|
||||
if (gate_id >= SUN6I_APB0_GATES_MAX_SIZE)
|
||||
continue;
|
||||
|
||||
clk_data->clks[gate_id] = clk_register_gate(&pdev->dev,
|
||||
clk_name,
|
||||
clk_parent, 0,
|
||||
reg, gate_id,
|
||||
0, NULL);
|
||||
WARN_ON(IS_ERR(clk_data->clks[gate_id]));
|
||||
}
|
||||
|
||||
clk_data->clk_num = ngates;
|
||||
|
||||
return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
|
||||
{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct platform_driver sun6i_a31_apb0_gates_clk_driver = {
|
||||
.driver = {
|
||||
.name = "sun6i-a31-apb0-gates-clk",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = sun6i_a31_apb0_gates_clk_dt_ids,
|
||||
},
|
||||
.probe = sun6i_a31_apb0_gates_clk_probe,
|
||||
};
|
||||
module_platform_driver(sun6i_a31_apb0_gates_clk_driver);
|
||||
|
||||
MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
|
||||
MODULE_DESCRIPTION("Allwinner A31 APB0 gate clocks driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
77
drivers/clk/sunxi/clk-sun6i-apb0.c
Normal file
77
drivers/clk/sunxi/clk-sun6i-apb0.c
Normal file
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Free Electrons
|
||||
*
|
||||
* License Terms: GNU General Public License v2
|
||||
* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
|
||||
*
|
||||
* Allwinner A31 APB0 clock driver
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
/*
|
||||
* The APB0 clk has a configurable divisor.
|
||||
*
|
||||
* We must use a clk_div_table and not a regular power of 2
|
||||
* divisor here, because the first 2 values divide the clock
|
||||
* by 2.
|
||||
*/
|
||||
static const struct clk_div_table sun6i_a31_apb0_divs[] = {
|
||||
{ .val = 0, .div = 2, },
|
||||
{ .val = 1, .div = 2, },
|
||||
{ .val = 2, .div = 4, },
|
||||
{ .val = 3, .div = 8, },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int sun6i_a31_apb0_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
const char *clk_name = np->name;
|
||||
const char *clk_parent;
|
||||
struct resource *r;
|
||||
void __iomem *reg;
|
||||
struct clk *clk;
|
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
reg = devm_ioremap_resource(&pdev->dev, r);
|
||||
if (IS_ERR(reg))
|
||||
return PTR_ERR(reg);
|
||||
|
||||
clk_parent = of_clk_get_parent_name(np, 0);
|
||||
if (!clk_parent)
|
||||
return -EINVAL;
|
||||
|
||||
of_property_read_string(np, "clock-output-names", &clk_name);
|
||||
|
||||
clk = clk_register_divider_table(&pdev->dev, clk_name, clk_parent,
|
||||
0, reg, 0, 2, 0, sun6i_a31_apb0_divs,
|
||||
NULL);
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
return of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||
}
|
||||
|
||||
const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = {
|
||||
{ .compatible = "allwinner,sun6i-a31-apb0-clk" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct platform_driver sun6i_a31_apb0_clk_driver = {
|
||||
.driver = {
|
||||
.name = "sun6i-a31-apb0-clk",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = sun6i_a31_apb0_clk_dt_ids,
|
||||
},
|
||||
.probe = sun6i_a31_apb0_clk_probe,
|
||||
};
|
||||
module_platform_driver(sun6i_a31_apb0_clk_driver);
|
||||
|
||||
MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
|
||||
MODULE_DESCRIPTION("Allwinner A31 APB0 clock Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
233
drivers/clk/sunxi/clk-sun6i-ar100.c
Normal file
233
drivers/clk/sunxi/clk-sun6i-ar100.c
Normal file
@ -0,0 +1,233 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Free Electrons
|
||||
*
|
||||
* License Terms: GNU General Public License v2
|
||||
* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
|
||||
*
|
||||
* Allwinner A31 AR100 clock driver
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#define SUN6I_AR100_MAX_PARENTS 4
|
||||
#define SUN6I_AR100_SHIFT_MASK 0x3
|
||||
#define SUN6I_AR100_SHIFT_MAX SUN6I_AR100_SHIFT_MASK
|
||||
#define SUN6I_AR100_SHIFT_SHIFT 4
|
||||
#define SUN6I_AR100_DIV_MASK 0x1f
|
||||
#define SUN6I_AR100_DIV_MAX (SUN6I_AR100_DIV_MASK + 1)
|
||||
#define SUN6I_AR100_DIV_SHIFT 8
|
||||
#define SUN6I_AR100_MUX_MASK 0x3
|
||||
#define SUN6I_AR100_MUX_SHIFT 16
|
||||
|
||||
struct ar100_clk {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
};
|
||||
|
||||
static inline struct ar100_clk *to_ar100_clk(struct clk_hw *hw)
|
||||
{
|
||||
return container_of(hw, struct ar100_clk, hw);
|
||||
}
|
||||
|
||||
static unsigned long ar100_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct ar100_clk *clk = to_ar100_clk(hw);
|
||||
u32 val = readl(clk->reg);
|
||||
int shift = (val >> SUN6I_AR100_SHIFT_SHIFT) & SUN6I_AR100_SHIFT_MASK;
|
||||
int div = (val >> SUN6I_AR100_DIV_SHIFT) & SUN6I_AR100_DIV_MASK;
|
||||
|
||||
return (parent_rate >> shift) / (div + 1);
|
||||
}
|
||||
|
||||
static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *best_parent_rate,
|
||||
struct clk **best_parent_clk)
|
||||
{
|
||||
int nparents = __clk_get_num_parents(hw->clk);
|
||||
long best_rate = -EINVAL;
|
||||
int i;
|
||||
|
||||
*best_parent_clk = NULL;
|
||||
|
||||
for (i = 0; i < nparents; i++) {
|
||||
unsigned long parent_rate;
|
||||
unsigned long tmp_rate;
|
||||
struct clk *parent;
|
||||
unsigned long div;
|
||||
int shift;
|
||||
|
||||
parent = clk_get_parent_by_index(hw->clk, i);
|
||||
parent_rate = __clk_get_rate(parent);
|
||||
div = DIV_ROUND_UP(parent_rate, rate);
|
||||
|
||||
/*
|
||||
* The AR100 clk contains 2 divisors:
|
||||
* - one power of 2 divisor
|
||||
* - one regular divisor
|
||||
*
|
||||
* First check if we can safely shift (or divide by a power
|
||||
* of 2) without losing precision on the requested rate.
|
||||
*/
|
||||
shift = ffs(div) - 1;
|
||||
if (shift > SUN6I_AR100_SHIFT_MAX)
|
||||
shift = SUN6I_AR100_SHIFT_MAX;
|
||||
|
||||
div >>= shift;
|
||||
|
||||
/*
|
||||
* Then if the divisor is still bigger than what the HW
|
||||
* actually supports, use a bigger shift (or power of 2
|
||||
* divider) value and accept to lose some precision.
|
||||
*/
|
||||
while (div > SUN6I_AR100_DIV_MAX) {
|
||||
shift++;
|
||||
div >>= 1;
|
||||
if (shift > SUN6I_AR100_SHIFT_MAX)
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* If the shift value (or power of 2 divider) is bigger
|
||||
* than what the HW actually support, skip this parent.
|
||||
*/
|
||||
if (shift > SUN6I_AR100_SHIFT_MAX)
|
||||
continue;
|
||||
|
||||
tmp_rate = (parent_rate >> shift) / div;
|
||||
if (!*best_parent_clk || tmp_rate > best_rate) {
|
||||
*best_parent_clk = parent;
|
||||
*best_parent_rate = parent_rate;
|
||||
best_rate = tmp_rate;
|
||||
}
|
||||
}
|
||||
|
||||
return best_rate;
|
||||
}
|
||||
|
||||
static int ar100_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct ar100_clk *clk = to_ar100_clk(hw);
|
||||
u32 val = readl(clk->reg);
|
||||
|
||||
if (index >= SUN6I_AR100_MAX_PARENTS)
|
||||
return -EINVAL;
|
||||
|
||||
val &= ~(SUN6I_AR100_MUX_MASK << SUN6I_AR100_MUX_SHIFT);
|
||||
val |= (index << SUN6I_AR100_MUX_SHIFT);
|
||||
writel(val, clk->reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u8 ar100_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct ar100_clk *clk = to_ar100_clk(hw);
|
||||
return (readl(clk->reg) >> SUN6I_AR100_MUX_SHIFT) &
|
||||
SUN6I_AR100_MUX_MASK;
|
||||
}
|
||||
|
||||
static int ar100_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned long div = parent_rate / rate;
|
||||
struct ar100_clk *clk = to_ar100_clk(hw);
|
||||
u32 val = readl(clk->reg);
|
||||
int shift;
|
||||
|
||||
if (parent_rate % rate)
|
||||
return -EINVAL;
|
||||
|
||||
shift = ffs(div) - 1;
|
||||
if (shift > SUN6I_AR100_SHIFT_MAX)
|
||||
shift = SUN6I_AR100_SHIFT_MAX;
|
||||
|
||||
div >>= shift;
|
||||
|
||||
if (div > SUN6I_AR100_DIV_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
val &= ~((SUN6I_AR100_SHIFT_MASK << SUN6I_AR100_SHIFT_SHIFT) |
|
||||
(SUN6I_AR100_DIV_MASK << SUN6I_AR100_DIV_SHIFT));
|
||||
val |= (shift << SUN6I_AR100_SHIFT_SHIFT) |
|
||||
(div << SUN6I_AR100_DIV_SHIFT);
|
||||
writel(val, clk->reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct clk_ops ar100_ops = {
|
||||
.recalc_rate = ar100_recalc_rate,
|
||||
.determine_rate = ar100_determine_rate,
|
||||
.set_parent = ar100_set_parent,
|
||||
.get_parent = ar100_get_parent,
|
||||
.set_rate = ar100_set_rate,
|
||||
};
|
||||
|
||||
static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
const char *parents[SUN6I_AR100_MAX_PARENTS];
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
const char *clk_name = np->name;
|
||||
struct clk_init_data init;
|
||||
struct ar100_clk *ar100;
|
||||
struct resource *r;
|
||||
struct clk *clk;
|
||||
int nparents;
|
||||
int i;
|
||||
|
||||
ar100 = devm_kzalloc(&pdev->dev, sizeof(*ar100), GFP_KERNEL);
|
||||
if (!ar100)
|
||||
return -ENOMEM;
|
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
ar100->reg = devm_ioremap_resource(&pdev->dev, r);
|
||||
if (IS_ERR(ar100->reg))
|
||||
return PTR_ERR(ar100->reg);
|
||||
|
||||
nparents = of_clk_get_parent_count(np);
|
||||
if (nparents > SUN6I_AR100_MAX_PARENTS)
|
||||
nparents = SUN6I_AR100_MAX_PARENTS;
|
||||
|
||||
for (i = 0; i < nparents; i++)
|
||||
parents[i] = of_clk_get_parent_name(np, i);
|
||||
|
||||
of_property_read_string(np, "clock-output-names", &clk_name);
|
||||
|
||||
init.name = clk_name;
|
||||
init.ops = &ar100_ops;
|
||||
init.parent_names = parents;
|
||||
init.num_parents = nparents;
|
||||
init.flags = 0;
|
||||
|
||||
ar100->hw.init = &init;
|
||||
|
||||
clk = clk_register(&pdev->dev, &ar100->hw);
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
return of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||
}
|
||||
|
||||
const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = {
|
||||
{ .compatible = "allwinner,sun6i-a31-ar100-clk" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct platform_driver sun6i_a31_ar100_clk_driver = {
|
||||
.driver = {
|
||||
.name = "sun6i-a31-ar100-clk",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = sun6i_a31_ar100_clk_dt_ids,
|
||||
},
|
||||
.probe = sun6i_a31_ar100_clk_probe,
|
||||
};
|
||||
module_platform_driver(sun6i_a31_ar100_clk_driver);
|
||||
|
||||
MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
|
||||
MODULE_DESCRIPTION("Allwinner A31 AR100 clock Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -27,63 +27,6 @@ static DEFINE_SPINLOCK(clk_lock);
|
||||
/* Maximum number of parents our clocks have */
|
||||
#define SUNXI_MAX_PARENTS 5
|
||||
|
||||
/**
|
||||
* sun4i_osc_clk_setup() - Setup function for gatable oscillator
|
||||
*/
|
||||
|
||||
#define SUNXI_OSC24M_GATE 0
|
||||
|
||||
static void __init sun4i_osc_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_fixed_rate *fixed;
|
||||
struct clk_gate *gate;
|
||||
const char *clk_name = node->name;
|
||||
u32 rate;
|
||||
|
||||
if (of_property_read_u32(node, "clock-frequency", &rate))
|
||||
return;
|
||||
|
||||
/* allocate fixed-rate and gate clock structs */
|
||||
fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
|
||||
if (!fixed)
|
||||
return;
|
||||
gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
|
||||
if (!gate)
|
||||
goto err_free_fixed;
|
||||
|
||||
of_property_read_string(node, "clock-output-names", &clk_name);
|
||||
|
||||
/* set up gate and fixed rate properties */
|
||||
gate->reg = of_iomap(node, 0);
|
||||
gate->bit_idx = SUNXI_OSC24M_GATE;
|
||||
gate->lock = &clk_lock;
|
||||
fixed->fixed_rate = rate;
|
||||
|
||||
clk = clk_register_composite(NULL, clk_name,
|
||||
NULL, 0,
|
||||
NULL, NULL,
|
||||
&fixed->hw, &clk_fixed_rate_ops,
|
||||
&gate->hw, &clk_gate_ops,
|
||||
CLK_IS_ROOT);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
goto err_free_gate;
|
||||
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
clk_register_clkdev(clk, clk_name, NULL);
|
||||
|
||||
return;
|
||||
|
||||
err_free_gate:
|
||||
kfree(gate);
|
||||
err_free_fixed:
|
||||
kfree(fixed);
|
||||
}
|
||||
CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-a10-osc-clk", sun4i_osc_clk_setup);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
|
||||
* PLL1 rate is calculated as follows
|
||||
@ -408,104 +351,6 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
|
||||
*p = calcp;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
|
||||
*
|
||||
* This clock looks something like this
|
||||
* ________________________
|
||||
* MII TX clock from PHY >-----|___________ _________|----> to GMAC core
|
||||
* GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
|
||||
* Ext. 125MHz RGMII TX clk >--|__divider__/ |
|
||||
* |________________________|
|
||||
*
|
||||
* The external 125 MHz reference is optional, i.e. GMAC can use its
|
||||
* internal TX clock just fine. The A31 GMAC clock module does not have
|
||||
* the divider controls for the external reference.
|
||||
*
|
||||
* To keep it simple, let the GMAC use either the MII TX clock for MII mode,
|
||||
* and its internal TX clock for GMII and RGMII modes. The GMAC driver should
|
||||
* select the appropriate source and gate/ungate the output to the PHY.
|
||||
*
|
||||
* Only the GMAC should use this clock. Altering the clock so that it doesn't
|
||||
* match the GMAC's operation parameters will result in the GMAC not being
|
||||
* able to send traffic out. The GMAC driver should set the clock rate and
|
||||
* enable/disable this clock to configure the required state. The clock
|
||||
* driver then responds by auto-reparenting the clock.
|
||||
*/
|
||||
|
||||
#define SUN7I_A20_GMAC_GPIT 2
|
||||
#define SUN7I_A20_GMAC_MASK 0x3
|
||||
#define SUN7I_A20_GMAC_PARENTS 2
|
||||
|
||||
static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_mux *mux;
|
||||
struct clk_gate *gate;
|
||||
const char *clk_name = node->name;
|
||||
const char *parents[SUN7I_A20_GMAC_PARENTS];
|
||||
void *reg;
|
||||
|
||||
if (of_property_read_string(node, "clock-output-names", &clk_name))
|
||||
return;
|
||||
|
||||
/* allocate mux and gate clock structs */
|
||||
mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
|
||||
if (!mux)
|
||||
return;
|
||||
|
||||
gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
|
||||
if (!gate)
|
||||
goto free_mux;
|
||||
|
||||
/* gmac clock requires exactly 2 parents */
|
||||
parents[0] = of_clk_get_parent_name(node, 0);
|
||||
parents[1] = of_clk_get_parent_name(node, 1);
|
||||
if (!parents[0] || !parents[1])
|
||||
goto free_gate;
|
||||
|
||||
reg = of_iomap(node, 0);
|
||||
if (!reg)
|
||||
goto free_gate;
|
||||
|
||||
/* set up gate and fixed rate properties */
|
||||
gate->reg = reg;
|
||||
gate->bit_idx = SUN7I_A20_GMAC_GPIT;
|
||||
gate->lock = &clk_lock;
|
||||
mux->reg = reg;
|
||||
mux->mask = SUN7I_A20_GMAC_MASK;
|
||||
mux->flags = CLK_MUX_INDEX_BIT;
|
||||
mux->lock = &clk_lock;
|
||||
|
||||
clk = clk_register_composite(NULL, clk_name,
|
||||
parents, SUN7I_A20_GMAC_PARENTS,
|
||||
&mux->hw, &clk_mux_ops,
|
||||
NULL, NULL,
|
||||
&gate->hw, &clk_gate_ops,
|
||||
0);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
goto iounmap_reg;
|
||||
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
clk_register_clkdev(clk, clk_name, NULL);
|
||||
|
||||
return;
|
||||
|
||||
iounmap_reg:
|
||||
iounmap(reg);
|
||||
free_gate:
|
||||
kfree(gate);
|
||||
free_mux:
|
||||
kfree(mux);
|
||||
}
|
||||
CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
|
||||
sun7i_a20_gmac_clk_setup);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* clk_sunxi_mmc_phase_control() - configures MMC clock phase control
|
||||
*/
|
||||
@ -1009,6 +854,11 @@ static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
|
||||
.reset_mask = 0x03,
|
||||
};
|
||||
|
||||
static const struct gates_data sun6i_a31_usb_gates_data __initconst = {
|
||||
.mask = { BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8) },
|
||||
.reset_mask = BIT(2) | BIT(1) | BIT(0),
|
||||
};
|
||||
|
||||
static void __init sunxi_gates_clk_setup(struct device_node *node,
|
||||
struct gates_data *data)
|
||||
{
|
||||
@ -1304,6 +1154,7 @@ static const struct of_device_id clk_gates_match[] __initconst = {
|
||||
{.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
|
||||
{.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
|
||||
{.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
|
||||
{.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,},
|
||||
{}
|
||||
};
|
||||
|
||||
@ -1321,33 +1172,10 @@ static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_mat
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* System clock protection
|
||||
*
|
||||
* By enabling these critical clocks, we prevent their accidental gating
|
||||
* by the framework
|
||||
*/
|
||||
static void __init sunxi_clock_protect(void)
|
||||
static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
|
||||
{
|
||||
struct clk *clk;
|
||||
unsigned int i;
|
||||
|
||||
/* memory bus clock - sun5i+ */
|
||||
clk = clk_get(NULL, "mbus");
|
||||
if (!IS_ERR(clk)) {
|
||||
clk_prepare_enable(clk);
|
||||
clk_put(clk);
|
||||
}
|
||||
|
||||
/* DDR clock - sun4i+ */
|
||||
clk = clk_get(NULL, "pll5_ddr");
|
||||
if (!IS_ERR(clk)) {
|
||||
clk_prepare_enable(clk);
|
||||
clk_put(clk);
|
||||
}
|
||||
}
|
||||
|
||||
static void __init sunxi_init_clocks(struct device_node *np)
|
||||
{
|
||||
/* Register factor clocks */
|
||||
of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
|
||||
|
||||
@ -1363,11 +1191,48 @@ static void __init sunxi_init_clocks(struct device_node *np)
|
||||
/* Register gate clocks */
|
||||
of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
|
||||
|
||||
/* Enable core system clocks */
|
||||
sunxi_clock_protect();
|
||||
/* Protect the clocks that needs to stay on */
|
||||
for (i = 0; i < nclocks; i++) {
|
||||
struct clk *clk = clk_get(NULL, clocks[i]);
|
||||
|
||||
if (!IS_ERR(clk))
|
||||
clk_prepare_enable(clk);
|
||||
}
|
||||
}
|
||||
CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
|
||||
CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);
|
||||
CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks);
|
||||
CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks);
|
||||
CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks);
|
||||
|
||||
static const char *sun4i_a10_critical_clocks[] __initdata = {
|
||||
"pll5_ddr",
|
||||
};
|
||||
|
||||
static void __init sun4i_a10_init_clocks(struct device_node *node)
|
||||
{
|
||||
sunxi_init_clocks(sun4i_a10_critical_clocks,
|
||||
ARRAY_SIZE(sun4i_a10_critical_clocks));
|
||||
}
|
||||
CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
|
||||
|
||||
static const char *sun5i_critical_clocks[] __initdata = {
|
||||
"mbus",
|
||||
"pll5_ddr",
|
||||
};
|
||||
|
||||
static void __init sun5i_init_clocks(struct device_node *node)
|
||||
{
|
||||
sunxi_init_clocks(sun5i_critical_clocks,
|
||||
ARRAY_SIZE(sun5i_critical_clocks));
|
||||
}
|
||||
CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
|
||||
CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
|
||||
CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
|
||||
|
||||
static const char *sun6i_critical_clocks[] __initdata = {
|
||||
"cpu",
|
||||
"ahb1_sdram",
|
||||
};
|
||||
|
||||
static void __init sun6i_init_clocks(struct device_node *node)
|
||||
{
|
||||
sunxi_init_clocks(sun6i_critical_clocks,
|
||||
ARRAY_SIZE(sun6i_critical_clocks));
|
||||
}
|
||||
CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user