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clk: meson: mpll: use 64bit math in rate_from_params

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On Meson8b the MPLL parent clock (fixed_pll) has a rate of 2550MHz.
Multiplying this with SDM_DEN results in a value greater than 32bits.
This is not a problem on the 64bit Meson GX SoCs, but it may result in
undefined behavior on the older 32bit Meson8b SoC.

While rate_from_params was only introduced recently to make the math
reusable from _round_rate and _recalc_rate the original bug exists much
longer.

Fixes: 1c50da4f27 ("clk: meson: add mpll support")
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[as discussed on the ml, use DIV_ROUND_UP_ULL]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Martin Blumenstingl 2017-04-01 15:02:25 +02:00 committed by Jerome Brunet
parent 88e4ac68ea
commit b609338b26
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/meson/clk-mpll.c
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@ -79,7 +79,7 @@ static long rate_from_params(unsigned long parent_rate,
if (n2 < N2_MIN) if (n2 < N2_MIN)
return -EINVAL; return -EINVAL;
return (parent_rate * SDM_DEN) / divisor; return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
} }
static void params_from_rate(unsigned long requested_rate, static void params_from_rate(unsigned long requested_rate,