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mmc: davinci_mmc: convert to DMA engine API
Removes use of the DaVinci EDMA private DMA API and replaces it with use of the DMA engine API. Signed-off-by: Matt Porter <mporter@ti.com> Tested-by: Tom Rini <trini@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
Matt Porter
Vinod Koul
parent
c2dde5f8f2
commit
b5daabbd3d
@ -30,11 +30,12 @@
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/edma.h>
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#include <linux/mmc/mmc.h>
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#include <mach/mmc.h>
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#include <mach/edma.h>
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/*
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* Register Definitions
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@ -200,21 +201,13 @@ struct mmc_davinci_host {
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u32 bytes_left;
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u32 rxdma, txdma;
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struct dma_chan *dma_tx;
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struct dma_chan *dma_rx;
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bool use_dma;
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bool do_dma;
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bool sdio_int;
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bool active_request;
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/* Scatterlist DMA uses one or more parameter RAM entries:
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* the main one (associated with rxdma or txdma) plus zero or
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* more links. The entries for a given transfer differ only
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* by memory buffer (address, length) and link field.
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*/
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struct edmacc_param tx_template;
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struct edmacc_param rx_template;
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unsigned n_link;
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u32 links[MAX_NR_SG - 1];
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/* For PIO we walk scatterlists one segment at a time. */
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unsigned int sg_len;
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struct scatterlist *sg;
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@ -410,153 +403,74 @@ static void mmc_davinci_start_command(struct mmc_davinci_host *host,
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static void davinci_abort_dma(struct mmc_davinci_host *host)
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{
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int sync_dev;
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struct dma_chan *sync_dev;
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if (host->data_dir == DAVINCI_MMC_DATADIR_READ)
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sync_dev = host->rxdma;
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sync_dev = host->dma_rx;
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else
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sync_dev = host->txdma;
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sync_dev = host->dma_tx;
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edma_stop(sync_dev);
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edma_clean_channel(sync_dev);
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dmaengine_terminate_all(sync_dev);
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}
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static void
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mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data);
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static void mmc_davinci_dma_cb(unsigned channel, u16 ch_status, void *data)
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{
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if (DMA_COMPLETE != ch_status) {
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struct mmc_davinci_host *host = data;
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/* Currently means: DMA Event Missed, or "null" transfer
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* request was seen. In the future, TC errors (like bad
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* addresses) might be presented too.
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*/
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dev_warn(mmc_dev(host->mmc), "DMA %s error\n",
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(host->data->flags & MMC_DATA_WRITE)
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? "write" : "read");
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host->data->error = -EIO;
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mmc_davinci_xfer_done(host, host->data);
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}
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}
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/* Set up tx or rx template, to be modified and updated later */
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static void __init mmc_davinci_dma_setup(struct mmc_davinci_host *host,
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bool tx, struct edmacc_param *template)
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{
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unsigned sync_dev;
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const u16 acnt = 4;
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const u16 bcnt = rw_threshold >> 2;
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const u16 ccnt = 0;
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u32 src_port = 0;
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u32 dst_port = 0;
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s16 src_bidx, dst_bidx;
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s16 src_cidx, dst_cidx;
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/*
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* A-B Sync transfer: each DMA request is for one "frame" of
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* rw_threshold bytes, broken into "acnt"-size chunks repeated
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* "bcnt" times. Each segment needs "ccnt" such frames; since
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* we tell the block layer our mmc->max_seg_size limit, we can
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* trust (later) that it's within bounds.
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*
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* The FIFOs are read/written in 4-byte chunks (acnt == 4) and
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* EDMA will optimize memory operations to use larger bursts.
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*/
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if (tx) {
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sync_dev = host->txdma;
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/* src_prt, ccnt, and link to be set up later */
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src_bidx = acnt;
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src_cidx = acnt * bcnt;
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dst_port = host->mem_res->start + DAVINCI_MMCDXR;
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dst_bidx = 0;
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dst_cidx = 0;
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} else {
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sync_dev = host->rxdma;
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src_port = host->mem_res->start + DAVINCI_MMCDRR;
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src_bidx = 0;
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src_cidx = 0;
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/* dst_prt, ccnt, and link to be set up later */
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dst_bidx = acnt;
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dst_cidx = acnt * bcnt;
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}
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/*
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* We can't use FIFO mode for the FIFOs because MMC FIFO addresses
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* are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT
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* parameter is ignored.
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*/
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edma_set_src(sync_dev, src_port, INCR, W8BIT);
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edma_set_dest(sync_dev, dst_port, INCR, W8BIT);
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edma_set_src_index(sync_dev, src_bidx, src_cidx);
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edma_set_dest_index(sync_dev, dst_bidx, dst_cidx);
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edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC);
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edma_read_slot(sync_dev, template);
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/* don't bother with irqs or chaining */
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template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12;
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}
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static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
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static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
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struct mmc_data *data)
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{
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struct edmacc_param *template;
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int channel, slot;
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unsigned link;
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struct scatterlist *sg;
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unsigned sg_len;
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unsigned bytes_left = host->bytes_left;
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const unsigned shift = ffs(rw_threshold) - 1;
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struct dma_chan *chan;
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struct dma_async_tx_descriptor *desc;
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int ret = 0;
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if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
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template = &host->tx_template;
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channel = host->txdma;
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struct dma_slave_config dma_tx_conf = {
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.direction = DMA_MEM_TO_DEV,
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.dst_addr = host->mem_res->start + DAVINCI_MMCDXR,
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.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
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.dst_maxburst =
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rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
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};
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chan = host->dma_tx;
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dmaengine_slave_config(host->dma_tx, &dma_tx_conf);
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desc = dmaengine_prep_slave_sg(host->dma_tx,
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data->sg,
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host->sg_len,
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DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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dev_dbg(mmc_dev(host->mmc),
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"failed to allocate DMA TX descriptor");
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ret = -1;
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goto out;
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}
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} else {
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template = &host->rx_template;
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channel = host->rxdma;
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struct dma_slave_config dma_rx_conf = {
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.direction = DMA_DEV_TO_MEM,
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.src_addr = host->mem_res->start + DAVINCI_MMCDRR,
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.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
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.src_maxburst =
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rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
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};
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chan = host->dma_rx;
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dmaengine_slave_config(host->dma_rx, &dma_rx_conf);
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desc = dmaengine_prep_slave_sg(host->dma_rx,
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data->sg,
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host->sg_len,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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dev_dbg(mmc_dev(host->mmc),
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"failed to allocate DMA RX descriptor");
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ret = -1;
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goto out;
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}
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}
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/* We know sg_len and ccnt will never be out of range because
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* we told the mmc layer which in turn tells the block layer
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* to ensure that it only hands us one scatterlist segment
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* per EDMA PARAM entry. Update the PARAM
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* entries needed for each segment of this scatterlist.
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*/
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for (slot = channel, link = 0, sg = data->sg, sg_len = host->sg_len;
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sg_len-- != 0 && bytes_left;
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sg = sg_next(sg), slot = host->links[link++]) {
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u32 buf = sg_dma_address(sg);
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unsigned count = sg_dma_len(sg);
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dmaengine_submit(desc);
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dma_async_issue_pending(chan);
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template->link_bcntrld = sg_len
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? (EDMA_CHAN_SLOT(host->links[link]) << 5)
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: 0xffff;
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if (count > bytes_left)
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count = bytes_left;
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bytes_left -= count;
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if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
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template->src = buf;
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else
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template->dst = buf;
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template->ccnt = count >> shift;
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edma_write_slot(slot, template);
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}
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if (host->version == MMC_CTLR_VERSION_2)
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edma_clear_event(channel);
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edma_start(channel);
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out:
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return ret;
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}
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static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
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@ -564,6 +478,7 @@ static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
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{
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int i;
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int mask = rw_threshold - 1;
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int ret = 0;
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host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
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((data->flags & MMC_DATA_WRITE)
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@ -583,70 +498,48 @@ static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
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}
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host->do_dma = 1;
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mmc_davinci_send_dma_request(host, data);
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ret = mmc_davinci_send_dma_request(host, data);
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return 0;
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return ret;
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}
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static void __init_or_module
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davinci_release_dma_channels(struct mmc_davinci_host *host)
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{
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unsigned i;
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if (!host->use_dma)
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return;
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for (i = 0; i < host->n_link; i++)
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edma_free_slot(host->links[i]);
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edma_free_channel(host->txdma);
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edma_free_channel(host->rxdma);
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dma_release_channel(host->dma_tx);
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dma_release_channel(host->dma_rx);
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}
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static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host)
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{
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u32 link_size;
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int r, i;
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int r;
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dma_cap_mask_t mask;
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/* Acquire master DMA write channel */
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r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host,
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EVENTQ_DEFAULT);
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if (r < 0) {
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dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
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"tx", r);
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return r;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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host->dma_tx =
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dma_request_channel(mask, edma_filter_fn, &host->txdma);
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if (!host->dma_tx) {
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dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n");
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return -ENODEV;
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}
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mmc_davinci_dma_setup(host, true, &host->tx_template);
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/* Acquire master DMA read channel */
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r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host,
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EVENTQ_DEFAULT);
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if (r < 0) {
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dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
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"rx", r);
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host->dma_rx =
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dma_request_channel(mask, edma_filter_fn, &host->rxdma);
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if (!host->dma_rx) {
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dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n");
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r = -ENODEV;
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goto free_master_write;
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}
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mmc_davinci_dma_setup(host, false, &host->rx_template);
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/* Allocate parameter RAM slots, which will later be bound to a
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* channel as needed to handle a scatterlist.
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*/
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link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links));
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for (i = 0; i < link_size; i++) {
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r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY);
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if (r < 0) {
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dev_dbg(mmc_dev(host->mmc), "dma PaRAM alloc --> %d\n",
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r);
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break;
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}
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host->links[i] = r;
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}
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host->n_link = i;
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return 0;
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free_master_write:
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edma_free_channel(host->txdma);
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dma_release_channel(host->dma_tx);
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return r;
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}
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@ -1359,7 +1252,7 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev)
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* Each hw_seg uses one EDMA parameter RAM slot, always one
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* channel and then usually some linked slots.
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*/
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mmc->max_segs = 1 + host->n_link;
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mmc->max_segs = MAX_NR_SG;
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/* EDMA limit per hw segment (one or two MBytes) */
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mmc->max_seg_size = MAX_CCNT * rw_threshold;
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