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staging: tidspbridge: remove dw_dmmu_base from cfg_hostres struct

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We don't need to map iva2 iommu register base address
anymore.

Signed-off-by: Fernando Guzman Lugo <x0095840@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Fernando Guzman Lugo 2010-10-05 15:35:41 -05:00 committed by Greg Kroah-Hartman
parent f94378f9f9
commit b5a4493923
4 changed files with 1 additions and 10 deletions
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3
drivers/staging/tidspbridge/core/tiomap3430.c
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@ -833,8 +833,6 @@ static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
iounmap((void *)host_res->dw_mem_base[3]); iounmap((void *)host_res->dw_mem_base[3]);
if (host_res->dw_mem_base[4]) if (host_res->dw_mem_base[4])
iounmap((void *)host_res->dw_mem_base[4]); iounmap((void *)host_res->dw_mem_base[4]);
if (host_res->dw_dmmu_base)
iounmap(host_res->dw_dmmu_base);
if (host_res->dw_per_base) if (host_res->dw_per_base)
iounmap(host_res->dw_per_base); iounmap(host_res->dw_per_base);
if (host_res->dw_per_pm_base) if (host_res->dw_per_pm_base)
@ -848,7 +846,6 @@ static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
host_res->dw_mem_base[2] = (u32) NULL; host_res->dw_mem_base[2] = (u32) NULL;
host_res->dw_mem_base[3] = (u32) NULL; host_res->dw_mem_base[3] = (u32) NULL;
host_res->dw_mem_base[4] = (u32) NULL; host_res->dw_mem_base[4] = (u32) NULL;
host_res->dw_dmmu_base = NULL;
host_res->dw_sys_ctrl_base = NULL; host_res->dw_sys_ctrl_base = NULL;
kfree(host_res); kfree(host_res);

3
drivers/staging/tidspbridge/core/tiomap_io.c
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@ -393,7 +393,6 @@ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val)
omap_dspbridge_dev->dev.platform_data; omap_dspbridge_dev->dev.platform_data;
struct cfg_hostres *resources = dev_context->resources; struct cfg_hostres *resources = dev_context->resources;
int status = 0; int status = 0;
u32 temp;
if (!dev_context->mbox) if (!dev_context->mbox)
return 0; return 0;
@ -437,7 +436,7 @@ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val)
omap_mbox_restore_ctx(dev_context->mbox); omap_mbox_restore_ctx(dev_context->mbox);
/* Access MMU SYS CONFIG register to generate a short wakeup */ /* Access MMU SYS CONFIG register to generate a short wakeup */
temp = readl(resources->dw_dmmu_base + 0x10); iommu_read_reg(dev_context->dsp_mmu, MMU_SYSCONFIG);
dev_context->dw_brd_state = BRD_RUNNING; dev_context->dw_brd_state = BRD_RUNNING;
} else if (dev_context->dw_brd_state == BRD_RETENTION) { } else if (dev_context->dw_brd_state == BRD_RETENTION) {

1
drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h
View File

@ -68,7 +68,6 @@ struct cfg_hostres {
void __iomem *dw_per_base; void __iomem *dw_per_base;
u32 dw_per_pm_base; u32 dw_per_pm_base;
u32 dw_core_pm_base; u32 dw_core_pm_base;
void __iomem *dw_dmmu_base;
void __iomem *dw_sys_ctrl_base; void __iomem *dw_sys_ctrl_base;
}; };

4
drivers/staging/tidspbridge/rmgr/drv.c
View File

@ -743,7 +743,6 @@ static int request_bridge_resources(struct cfg_hostres *res)
host_res->dw_sys_ctrl_base = ioremap(OMAP_SYSC_BASE, OMAP_SYSC_SIZE); host_res->dw_sys_ctrl_base = ioremap(OMAP_SYSC_BASE, OMAP_SYSC_SIZE);
dev_dbg(bridge, "dw_mem_base[0] 0x%x\n", host_res->dw_mem_base[0]); dev_dbg(bridge, "dw_mem_base[0] 0x%x\n", host_res->dw_mem_base[0]);
dev_dbg(bridge, "dw_mem_base[3] 0x%x\n", host_res->dw_mem_base[3]); dev_dbg(bridge, "dw_mem_base[3] 0x%x\n", host_res->dw_mem_base[3]);
dev_dbg(bridge, "dw_dmmu_base %p\n", host_res->dw_dmmu_base);
/* for 24xx base port is not mapping the mamory for DSP /* for 24xx base port is not mapping the mamory for DSP
* internal memory TODO Do a ioremap here */ * internal memory TODO Do a ioremap here */
@ -797,8 +796,6 @@ int drv_request_bridge_res_dsp(void **phost_resources)
OMAP_PER_PRM_SIZE); OMAP_PER_PRM_SIZE);
host_res->dw_core_pm_base = (u32) ioremap(OMAP_CORE_PRM_BASE, host_res->dw_core_pm_base = (u32) ioremap(OMAP_CORE_PRM_BASE,
OMAP_CORE_PRM_SIZE); OMAP_CORE_PRM_SIZE);
host_res->dw_dmmu_base = ioremap(OMAP_DMMU_BASE,
OMAP_DMMU_SIZE);
dev_dbg(bridge, "dw_mem_base[0] 0x%x\n", dev_dbg(bridge, "dw_mem_base[0] 0x%x\n",
host_res->dw_mem_base[0]); host_res->dw_mem_base[0]);
@ -810,7 +807,6 @@ int drv_request_bridge_res_dsp(void **phost_resources)
host_res->dw_mem_base[3]); host_res->dw_mem_base[3]);
dev_dbg(bridge, "dw_mem_base[4] 0x%x\n", dev_dbg(bridge, "dw_mem_base[4] 0x%x\n",
host_res->dw_mem_base[4]); host_res->dw_mem_base[4]);
dev_dbg(bridge, "dw_dmmu_base %p\n", host_res->dw_dmmu_base);
shm_size = drv_datap->shm_size; shm_size = drv_datap->shm_size;
if (shm_size >= 0x10000) { if (shm_size >= 0x10000) {