mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 07:46:51 +07:00
mtd: rawnand: Drop obsolete JZ4740 NAND driver
It has been replaced with the newer Ingenic NAND driver. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: Artur Rojek <contact@artur-rojek.eu> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com>
This commit is contained in:
Paul Cercueil
Paul Burton
parent
091c6104ad
commit
b58451e00f
@ -1,11 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config MTD_NAND_JZ4740
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tristate "JZ4740 NAND controller"
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depends on MACH_JZ4740 || COMPILE_TEST
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depends on HAS_IOMEM
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help
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Enables support for NAND Flash on JZ4740 SoC based boards.
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config MTD_NAND_JZ4780
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tristate "JZ4780 NAND controller"
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depends on JZ4780_NEMC
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@ -1,5 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
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obj-$(CONFIG_MTD_NAND_JZ4780) += ingenic_nand.o
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ingenic_nand-y += ingenic_nand_drv.o
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@ -1,536 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 SoC NAND controller driver
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*/
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/gpio/consumer.h>
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#include <linux/platform_data/jz4740/jz4740_nand.h>
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#define JZ_REG_NAND_CTRL 0x50
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#define JZ_REG_NAND_ECC_CTRL 0x100
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#define JZ_REG_NAND_DATA 0x104
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#define JZ_REG_NAND_PAR0 0x108
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#define JZ_REG_NAND_PAR1 0x10C
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#define JZ_REG_NAND_PAR2 0x110
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#define JZ_REG_NAND_IRQ_STAT 0x114
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#define JZ_REG_NAND_IRQ_CTRL 0x118
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#define JZ_REG_NAND_ERR(x) (0x11C + ((x) << 2))
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#define JZ_NAND_ECC_CTRL_PAR_READY BIT(4)
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#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
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#define JZ_NAND_ECC_CTRL_RS BIT(2)
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#define JZ_NAND_ECC_CTRL_RESET BIT(1)
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#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
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#define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29))
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#define JZ_NAND_STATUS_PAD_FINISH BIT(4)
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#define JZ_NAND_STATUS_DEC_FINISH BIT(3)
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#define JZ_NAND_STATUS_ENC_FINISH BIT(2)
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#define JZ_NAND_STATUS_UNCOR_ERROR BIT(1)
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#define JZ_NAND_STATUS_ERROR BIT(0)
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#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
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#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
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#define JZ_NAND_CTRL_ASSERT_CHIP_MASK 0xaa
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#define JZ_NAND_MEM_CMD_OFFSET 0x08000
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#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
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struct jz_nand {
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struct nand_chip chip;
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void __iomem *base;
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struct resource *mem;
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unsigned char banks[JZ_NAND_NUM_BANKS];
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void __iomem *bank_base[JZ_NAND_NUM_BANKS];
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struct resource *bank_mem[JZ_NAND_NUM_BANKS];
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int selected_bank;
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struct gpio_desc *busy_gpio;
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bool is_reading;
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};
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static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
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{
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return container_of(mtd_to_nand(mtd), struct jz_nand, chip);
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}
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static void jz_nand_select_chip(struct nand_chip *chip, int chipnr)
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{
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struct jz_nand *nand = mtd_to_jz_nand(nand_to_mtd(chip));
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uint32_t ctrl;
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int banknr;
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ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
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ctrl &= ~JZ_NAND_CTRL_ASSERT_CHIP_MASK;
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if (chipnr == -1) {
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banknr = -1;
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} else {
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banknr = nand->banks[chipnr] - 1;
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chip->legacy.IO_ADDR_R = nand->bank_base[banknr];
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chip->legacy.IO_ADDR_W = nand->bank_base[banknr];
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}
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writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
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nand->selected_bank = banknr;
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}
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static void jz_nand_cmd_ctrl(struct nand_chip *chip, int dat,
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unsigned int ctrl)
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{
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struct jz_nand *nand = mtd_to_jz_nand(nand_to_mtd(chip));
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uint32_t reg;
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void __iomem *bank_base = nand->bank_base[nand->selected_bank];
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BUG_ON(nand->selected_bank < 0);
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if (ctrl & NAND_CTRL_CHANGE) {
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BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
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if (ctrl & NAND_ALE)
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bank_base += JZ_NAND_MEM_ADDR_OFFSET;
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else if (ctrl & NAND_CLE)
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bank_base += JZ_NAND_MEM_CMD_OFFSET;
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chip->legacy.IO_ADDR_W = bank_base;
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reg = readl(nand->base + JZ_REG_NAND_CTRL);
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if (ctrl & NAND_NCE)
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reg |= JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
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else
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reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
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writel(reg, nand->base + JZ_REG_NAND_CTRL);
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}
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if (dat != NAND_CMD_NONE)
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writeb(dat, chip->legacy.IO_ADDR_W);
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}
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static int jz_nand_dev_ready(struct nand_chip *chip)
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{
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struct jz_nand *nand = mtd_to_jz_nand(nand_to_mtd(chip));
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return gpiod_get_value_cansleep(nand->busy_gpio);
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}
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static void jz_nand_hwctl(struct nand_chip *chip, int mode)
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{
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struct jz_nand *nand = mtd_to_jz_nand(nand_to_mtd(chip));
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uint32_t reg;
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writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg |= JZ_NAND_ECC_CTRL_RESET;
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reg |= JZ_NAND_ECC_CTRL_ENABLE;
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reg |= JZ_NAND_ECC_CTRL_RS;
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switch (mode) {
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case NAND_ECC_READ:
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reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
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nand->is_reading = true;
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break;
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case NAND_ECC_WRITE:
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reg |= JZ_NAND_ECC_CTRL_ENCODING;
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nand->is_reading = false;
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break;
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default:
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break;
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}
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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}
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static int jz_nand_calculate_ecc_rs(struct nand_chip *chip, const uint8_t *dat,
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uint8_t *ecc_code)
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{
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struct jz_nand *nand = mtd_to_jz_nand(nand_to_mtd(chip));
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uint32_t reg, status;
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int i;
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unsigned int timeout = 1000;
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static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4,
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0x8b, 0xff, 0xb7, 0x6f};
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if (nand->is_reading)
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return 0;
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do {
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status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
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} while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout);
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if (timeout == 0)
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return -1;
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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for (i = 0; i < 9; ++i)
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ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
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/* If the written data is completly 0xff, we also want to write 0xff as
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* ecc, otherwise we will get in trouble when doing subpage writes. */
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if (memcmp(ecc_code, empty_block_ecc, 9) == 0)
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memset(ecc_code, 0xff, 9);
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return 0;
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}
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static void jz_nand_correct_data(uint8_t *dat, int index, int mask)
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{
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int offset = index & 0x7;
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uint16_t data;
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index += (index >> 3);
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data = dat[index];
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data |= dat[index+1] << 8;
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mask ^= (data >> offset) & 0x1ff;
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data &= ~(0x1ff << offset);
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data |= (mask << offset);
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dat[index] = data & 0xff;
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dat[index+1] = (data >> 8) & 0xff;
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}
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static int jz_nand_correct_ecc_rs(struct nand_chip *chip, uint8_t *dat,
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uint8_t *read_ecc, uint8_t *calc_ecc)
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{
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struct jz_nand *nand = mtd_to_jz_nand(nand_to_mtd(chip));
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int i, error_count, index;
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uint32_t reg, status, error;
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unsigned int timeout = 1000;
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for (i = 0; i < 9; ++i)
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writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg |= JZ_NAND_ECC_CTRL_PAR_READY;
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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do {
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status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
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} while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout);
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if (timeout == 0)
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return -ETIMEDOUT;
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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if (status & JZ_NAND_STATUS_ERROR) {
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if (status & JZ_NAND_STATUS_UNCOR_ERROR)
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return -EBADMSG;
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error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
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for (i = 0; i < error_count; ++i) {
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error = readl(nand->base + JZ_REG_NAND_ERR(i));
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index = ((error >> 16) & 0x1ff) - 1;
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if (index >= 0 && index < 512)
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jz_nand_correct_data(dat, index, error & 0x1ff);
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}
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return error_count;
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}
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return 0;
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}
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static int jz_nand_ioremap_resource(struct platform_device *pdev,
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const char *name, struct resource **res, void __iomem **base)
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{
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int ret;
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*res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
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if (!*res) {
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dev_err(&pdev->dev, "Failed to get platform %s memory\n", name);
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ret = -ENXIO;
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goto err;
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}
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*res = request_mem_region((*res)->start, resource_size(*res),
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pdev->name);
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if (!*res) {
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dev_err(&pdev->dev, "Failed to request %s memory region\n", name);
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ret = -EBUSY;
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goto err;
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}
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*base = ioremap((*res)->start, resource_size(*res));
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if (!*base) {
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dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name);
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ret = -EBUSY;
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goto err_release_mem;
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}
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return 0;
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err_release_mem:
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release_mem_region((*res)->start, resource_size(*res));
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err:
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*res = NULL;
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*base = NULL;
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return ret;
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}
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static inline void jz_nand_iounmap_resource(struct resource *res,
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void __iomem *base)
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{
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iounmap(base);
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release_mem_region(res->start, resource_size(res));
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}
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static int jz_nand_detect_bank(struct platform_device *pdev,
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struct jz_nand *nand, unsigned char bank,
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size_t chipnr, uint8_t *nand_maf_id,
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uint8_t *nand_dev_id)
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{
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int ret;
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char res_name[6];
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uint32_t ctrl;
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struct nand_chip *chip = &nand->chip;
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct nand_memory_organization *memorg;
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u8 id[2];
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memorg = nanddev_get_memorg(&chip->base);
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/* Request I/O resource. */
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sprintf(res_name, "bank%d", bank);
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ret = jz_nand_ioremap_resource(pdev, res_name,
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&nand->bank_mem[bank - 1],
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&nand->bank_base[bank - 1]);
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if (ret)
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return ret;
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/* Enable chip in bank. */
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ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
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ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
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writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
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if (chipnr == 0) {
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/* Detect first chip. */
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ret = nand_scan(chip, 1);
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if (ret)
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goto notfound_id;
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/* Retrieve the IDs from the first chip. */
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nand_select_target(chip, 0);
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nand_reset_op(chip);
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nand_readid_op(chip, 0, id, sizeof(id));
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*nand_maf_id = id[0];
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*nand_dev_id = id[1];
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} else {
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/* Detect additional chip. */
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nand_select_target(chip, chipnr);
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nand_reset_op(chip);
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nand_readid_op(chip, 0, id, sizeof(id));
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if (*nand_maf_id != id[0] || *nand_dev_id != id[1]) {
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ret = -ENODEV;
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goto notfound_id;
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}
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/* Update size of the MTD. */
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memorg->ntargets++;
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mtd->size += nanddev_target_size(&chip->base);
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}
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dev_info(&pdev->dev, "Found chip %zu on bank %i\n", chipnr, bank);
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return 0;
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notfound_id:
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dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
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ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
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writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
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jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
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nand->bank_base[bank - 1]);
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return ret;
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}
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static int jz_nand_attach_chip(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct device *dev = mtd->dev.parent;
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struct jz_nand_platform_data *pdata = dev_get_platdata(dev);
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struct platform_device *pdev = to_platform_device(dev);
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if (pdata && pdata->ident_callback)
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pdata->ident_callback(pdev, mtd, &pdata->partitions,
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&pdata->num_partitions);
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return 0;
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}
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static const struct nand_controller_ops jz_nand_controller_ops = {
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.attach_chip = jz_nand_attach_chip,
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};
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static int jz_nand_probe(struct platform_device *pdev)
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{
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int ret;
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struct jz_nand *nand;
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struct nand_chip *chip;
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struct mtd_info *mtd;
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struct jz_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
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size_t chipnr, bank_idx;
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uint8_t nand_maf_id = 0, nand_dev_id = 0;
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nand = kzalloc(sizeof(*nand), GFP_KERNEL);
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if (!nand)
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return -ENOMEM;
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ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
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if (ret)
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goto err_free;
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nand->busy_gpio = devm_gpiod_get_optional(&pdev->dev, "busy", GPIOD_IN);
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if (IS_ERR(nand->busy_gpio)) {
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ret = PTR_ERR(nand->busy_gpio);
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dev_err(&pdev->dev, "Failed to request busy gpio %d\n",
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ret);
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goto err_iounmap_mmio;
|
||||
}
|
||||
|
||||
chip = &nand->chip;
|
||||
mtd = nand_to_mtd(chip);
|
||||
mtd->dev.parent = &pdev->dev;
|
||||
mtd->name = "jz4740-nand";
|
||||
|
||||
chip->ecc.hwctl = jz_nand_hwctl;
|
||||
chip->ecc.calculate = jz_nand_calculate_ecc_rs;
|
||||
chip->ecc.correct = jz_nand_correct_ecc_rs;
|
||||
chip->ecc.mode = NAND_ECC_HW_OOB_FIRST;
|
||||
chip->ecc.size = 512;
|
||||
chip->ecc.bytes = 9;
|
||||
chip->ecc.strength = 4;
|
||||
chip->ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
|
||||
|
||||
chip->legacy.chip_delay = 50;
|
||||
chip->legacy.cmd_ctrl = jz_nand_cmd_ctrl;
|
||||
chip->legacy.select_chip = jz_nand_select_chip;
|
||||
chip->legacy.dummy_controller.ops = &jz_nand_controller_ops;
|
||||
|
||||
if (nand->busy_gpio)
|
||||
chip->legacy.dev_ready = jz_nand_dev_ready;
|
||||
|
||||
platform_set_drvdata(pdev, nand);
|
||||
|
||||
/* We are going to autodetect NAND chips in the banks specified in the
|
||||
* platform data. Although nand_scan_ident() can detect multiple chips,
|
||||
* it requires those chips to be numbered consecuitively, which is not
|
||||
* always the case for external memory banks. And a fixed chip-to-bank
|
||||
* mapping is not practical either, since for example Dingoo units
|
||||
* produced at different times have NAND chips in different banks.
|
||||
*/
|
||||
chipnr = 0;
|
||||
for (bank_idx = 0; bank_idx < JZ_NAND_NUM_BANKS; bank_idx++) {
|
||||
unsigned char bank;
|
||||
|
||||
/* If there is no platform data, look for NAND in bank 1,
|
||||
* which is the most likely bank since it is the only one
|
||||
* that can be booted from.
|
||||
*/
|
||||
bank = pdata ? pdata->banks[bank_idx] : bank_idx ^ 1;
|
||||
if (bank == 0)
|
||||
break;
|
||||
if (bank > JZ_NAND_NUM_BANKS) {
|
||||
dev_warn(&pdev->dev,
|
||||
"Skipping non-existing bank: %d\n", bank);
|
||||
continue;
|
||||
}
|
||||
/* The detection routine will directly or indirectly call
|
||||
* jz_nand_select_chip(), so nand->banks has to contain the
|
||||
* bank we're checking.
|
||||
*/
|
||||
nand->banks[chipnr] = bank;
|
||||
if (jz_nand_detect_bank(pdev, nand, bank, chipnr,
|
||||
&nand_maf_id, &nand_dev_id) == 0)
|
||||
chipnr++;
|
||||
else
|
||||
nand->banks[chipnr] = 0;
|
||||
}
|
||||
if (chipnr == 0) {
|
||||
dev_err(&pdev->dev, "No NAND chips found\n");
|
||||
goto err_iounmap_mmio;
|
||||
}
|
||||
|
||||
ret = mtd_device_register(mtd, pdata ? pdata->partitions : NULL,
|
||||
pdata ? pdata->num_partitions : 0);
|
||||
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to add mtd device\n");
|
||||
goto err_cleanup_nand;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err_cleanup_nand:
|
||||
nand_cleanup(chip);
|
||||
while (chipnr--) {
|
||||
unsigned char bank = nand->banks[chipnr];
|
||||
jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
|
||||
nand->bank_base[bank - 1]);
|
||||
}
|
||||
writel(0, nand->base + JZ_REG_NAND_CTRL);
|
||||
err_iounmap_mmio:
|
||||
jz_nand_iounmap_resource(nand->mem, nand->base);
|
||||
err_free:
|
||||
kfree(nand);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int jz_nand_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct jz_nand *nand = platform_get_drvdata(pdev);
|
||||
size_t i;
|
||||
|
||||
nand_release(&nand->chip);
|
||||
|
||||
/* Deassert and disable all chips */
|
||||
writel(0, nand->base + JZ_REG_NAND_CTRL);
|
||||
|
||||
for (i = 0; i < JZ_NAND_NUM_BANKS; ++i) {
|
||||
unsigned char bank = nand->banks[i];
|
||||
if (bank != 0) {
|
||||
jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
|
||||
nand->bank_base[bank - 1]);
|
||||
}
|
||||
}
|
||||
|
||||
jz_nand_iounmap_resource(nand->mem, nand->base);
|
||||
|
||||
kfree(nand);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver jz_nand_driver = {
|
||||
.probe = jz_nand_probe,
|
||||
.remove = jz_nand_remove,
|
||||
.driver = {
|
||||
.name = "jz4740-nand",
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(jz_nand_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
||||
MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC");
|
||||
MODULE_ALIAS("platform:jz4740-nand");
|
||||
Loading…
Reference in New Issue
Block a user