mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 01:46:51 +07:00
Merge branch 'spi-5.0' into spi-linus
This commit is contained in:
commit
b50c6ac8b6
@ -54,41 +54,41 @@ static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
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if (!buf)
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return 0;
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"%s registers:\n", dev_name(&dws->master->dev));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"=================================\n");
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"=================================\n");
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ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
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@ -67,7 +67,7 @@
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#define SPI_SR 0x2c
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#define SPI_SR_EOQF 0x10000000
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#define SPI_SR_TCFQF 0x80000000
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#define SPI_SR_CLEAR 0xdaad0000
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#define SPI_SR_CLEAR 0x9aaf0000
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#define SPI_RSER_TFFFE BIT(25)
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#define SPI_RSER_TFFFD BIT(24)
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@ -48,10 +48,13 @@
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#define CR_RTF BIT(8)
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#define CR_RST BIT(1)
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#define CR_MEN BIT(0)
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#define SR_MBF BIT(24)
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#define SR_TCF BIT(10)
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#define SR_FCF BIT(9)
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#define SR_RDF BIT(1)
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#define SR_TDF BIT(0)
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#define IER_TCIE BIT(10)
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#define IER_FCIE BIT(9)
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#define IER_RDIE BIT(1)
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#define IER_TDIE BIT(0)
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#define CFGR1_PCSCFG BIT(27)
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@ -59,6 +62,7 @@
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#define CFGR1_PCSPOL BIT(8)
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#define CFGR1_NOSTALL BIT(3)
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#define CFGR1_MASTER BIT(0)
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#define FSR_RXCOUNT (BIT(16)|BIT(17)|BIT(18))
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#define RSR_RXEMPTY BIT(1)
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#define TCR_CPOL BIT(31)
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#define TCR_CPHA BIT(30)
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@ -161,28 +165,10 @@ static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
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return 0;
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}
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static int fsl_lpspi_txfifo_empty(struct fsl_lpspi_data *fsl_lpspi)
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{
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u32 txcnt;
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unsigned long orig_jiffies = jiffies;
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do {
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txcnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
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if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
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dev_dbg(fsl_lpspi->dev, "txfifo empty timeout\n");
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return -ETIMEDOUT;
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}
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cond_resched();
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} while (txcnt);
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return 0;
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}
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static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
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{
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u8 txfifo_cnt;
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u32 temp;
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txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
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@ -193,9 +179,15 @@ static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
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txfifo_cnt++;
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}
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if (!fsl_lpspi->remain && (txfifo_cnt < fsl_lpspi->txfifosize))
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writel(0, fsl_lpspi->base + IMX7ULP_TDR);
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else
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if (txfifo_cnt < fsl_lpspi->txfifosize) {
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if (!fsl_lpspi->is_slave) {
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temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
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temp &= ~TCR_CONTC;
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writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
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}
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fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
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} else
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fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
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}
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@ -276,10 +268,6 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
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u32 temp;
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int ret;
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temp = CR_RST;
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writel(temp, fsl_lpspi->base + IMX7ULP_CR);
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writel(0, fsl_lpspi->base + IMX7ULP_CR);
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if (!fsl_lpspi->is_slave) {
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ret = fsl_lpspi_set_bitrate(fsl_lpspi);
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if (ret)
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@ -370,6 +358,24 @@ static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
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return 0;
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}
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static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
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{
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u32 temp;
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/* Disable all interrupt */
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fsl_lpspi_intctrl(fsl_lpspi, 0);
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/* W1C for all flags in SR */
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temp = 0x3F << 8;
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writel(temp, fsl_lpspi->base + IMX7ULP_SR);
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/* Clear FIFO and disable module */
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temp = CR_RRF | CR_RTF;
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writel(temp, fsl_lpspi->base + IMX7ULP_CR);
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return 0;
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}
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static int fsl_lpspi_transfer_one(struct spi_controller *controller,
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struct spi_device *spi,
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struct spi_transfer *t)
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@ -391,11 +397,7 @@ static int fsl_lpspi_transfer_one(struct spi_controller *controller,
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if (ret)
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return ret;
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ret = fsl_lpspi_txfifo_empty(fsl_lpspi);
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if (ret)
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return ret;
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fsl_lpspi_read_rx_fifo(fsl_lpspi);
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fsl_lpspi_reset(fsl_lpspi);
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return 0;
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}
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@ -408,7 +410,6 @@ static int fsl_lpspi_transfer_one_msg(struct spi_controller *controller,
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struct spi_device *spi = msg->spi;
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struct spi_transfer *xfer;
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bool is_first_xfer = true;
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u32 temp;
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int ret = 0;
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msg->status = 0;
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@ -428,13 +429,6 @@ static int fsl_lpspi_transfer_one_msg(struct spi_controller *controller,
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}
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complete:
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if (!fsl_lpspi->is_slave) {
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/* de-assert SS, then finalize current message */
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temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
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temp &= ~TCR_CONTC;
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writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
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}
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msg->status = ret;
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spi_finalize_current_message(controller);
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@ -443,20 +437,30 @@ static int fsl_lpspi_transfer_one_msg(struct spi_controller *controller,
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static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
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{
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u32 temp_SR, temp_IER;
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struct fsl_lpspi_data *fsl_lpspi = dev_id;
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u32 temp;
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temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
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fsl_lpspi_intctrl(fsl_lpspi, 0);
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temp = readl(fsl_lpspi->base + IMX7ULP_SR);
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temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
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fsl_lpspi_read_rx_fifo(fsl_lpspi);
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if (temp & SR_TDF) {
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if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
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fsl_lpspi_write_tx_fifo(fsl_lpspi);
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return IRQ_HANDLED;
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}
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if (!fsl_lpspi->remain)
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if (temp_SR & SR_MBF ||
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readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_RXCOUNT) {
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writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
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fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
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return IRQ_HANDLED;
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}
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if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
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writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
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complete(&fsl_lpspi->xfer_done);
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return IRQ_HANDLED;
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}
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|
@ -428,7 +428,8 @@ static int spi_gpio_probe(struct platform_device *pdev)
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return status;
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
|
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master->mode_bits = SPI_3WIRE | SPI_3WIRE_HIZ | SPI_CPHA | SPI_CPOL;
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master->mode_bits = SPI_3WIRE | SPI_3WIRE_HIZ | SPI_CPHA | SPI_CPOL |
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SPI_CS_HIGH;
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master->flags = master_flags;
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master->bus_num = pdev->id;
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/* The master needs to think there is a chipselect even if not connected */
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@ -455,7 +456,6 @@ static int spi_gpio_probe(struct platform_device *pdev)
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||||
spi_gpio->bitbang.txrx_word[SPI_MODE_3] = spi_gpio_spec_txrx_word_mode3;
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}
|
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spi_gpio->bitbang.setup_transfer = spi_bitbang_setup_transfer;
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spi_gpio->bitbang.flags = SPI_CS_HIGH;
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|
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status = spi_bitbang_start(&spi_gpio->bitbang);
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if (status)
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||||
|
@ -537,7 +537,6 @@ EXPORT_SYMBOL_GPL(spi_mem_dirmap_create);
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/**
|
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* spi_mem_dirmap_destroy() - Destroy a direct mapping descriptor
|
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* @desc: the direct mapping descriptor to destroy
|
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* @info: direct mapping information
|
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*
|
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* This function destroys a direct mapping descriptor previously created by
|
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* spi_mem_dirmap_create().
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@ -548,6 +547,8 @@ void spi_mem_dirmap_destroy(struct spi_mem_dirmap_desc *desc)
|
||||
|
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if (!desc->nodirmap && ctlr->mem_ops && ctlr->mem_ops->dirmap_destroy)
|
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ctlr->mem_ops->dirmap_destroy(desc);
|
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|
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kfree(desc);
|
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}
|
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EXPORT_SYMBOL_GPL(spi_mem_dirmap_destroy);
|
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|
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|
@ -465,7 +465,8 @@ static int npcm_pspi_probe(struct platform_device *pdev)
|
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|
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static int npcm_pspi_remove(struct platform_device *pdev)
|
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{
|
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struct npcm_pspi *priv = platform_get_drvdata(pdev);
|
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struct spi_master *master = platform_get_drvdata(pdev);
|
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struct npcm_pspi *priv = spi_master_get_devdata(master);
|
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|
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npcm_pspi_reset_hw(priv);
|
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clk_disable_unprepare(priv->clk);
|
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|
@ -623,8 +623,8 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
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cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
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cfg.src_addr_width = width;
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cfg.dst_addr_width = width;
|
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cfg.src_maxburst = es;
|
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cfg.dst_maxburst = es;
|
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cfg.src_maxburst = 1;
|
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cfg.dst_maxburst = 1;
|
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|
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rx = xfer->rx_buf;
|
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tx = xfer->tx_buf;
|
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|
@ -1696,6 +1696,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
|
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platform_info->enable_dma = false;
|
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} else {
|
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master->can_dma = pxa2xx_spi_can_dma;
|
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master->max_dma_len = MAX_DMA_LEN;
|
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}
|
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}
|
||||
|
||||
|
@ -380,7 +380,7 @@ static int sprd_spi_txrx_bufs(struct spi_device *sdev, struct spi_transfer *t)
|
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{
|
||||
struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller);
|
||||
u32 trans_len = ss->trans_len, len;
|
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int ret, write_size = 0;
|
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int ret, write_size = 0, read_size = 0;
|
||||
|
||||
while (trans_len) {
|
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len = trans_len > SPRD_SPI_FIFO_SIZE ? SPRD_SPI_FIFO_SIZE :
|
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@ -416,13 +416,15 @@ static int sprd_spi_txrx_bufs(struct spi_device *sdev, struct spi_transfer *t)
|
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goto complete;
|
||||
|
||||
if (ss->trans_mode & SPRD_SPI_RX_MODE)
|
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ss->read_bufs(ss, len);
|
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read_size += ss->read_bufs(ss, len);
|
||||
|
||||
trans_len -= len;
|
||||
}
|
||||
|
||||
if (ss->trans_mode & SPRD_SPI_TX_MODE)
|
||||
ret = write_size;
|
||||
|
||||
else
|
||||
ret = read_size;
|
||||
complete:
|
||||
sprd_spi_enter_idle(ss);
|
||||
|
||||
|
@ -490,8 +490,8 @@ static void ti_qspi_enable_memory_map(struct spi_device *spi)
|
||||
ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
|
||||
if (qspi->ctrl_base) {
|
||||
regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
|
||||
MEM_CS_EN(spi->chip_select),
|
||||
MEM_CS_MASK);
|
||||
MEM_CS_MASK,
|
||||
MEM_CS_EN(spi->chip_select));
|
||||
}
|
||||
qspi->mmap_enabled = true;
|
||||
}
|
||||
@ -503,7 +503,7 @@ static void ti_qspi_disable_memory_map(struct spi_device *spi)
|
||||
ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
|
||||
if (qspi->ctrl_base)
|
||||
regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
|
||||
0, MEM_CS_MASK);
|
||||
MEM_CS_MASK, 0);
|
||||
qspi->mmap_enabled = false;
|
||||
}
|
||||
|
||||
|
@ -1008,6 +1008,9 @@ static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
|
||||
|
||||
/* RX */
|
||||
dma->sg_rx_p = kcalloc(num, sizeof(*dma->sg_rx_p), GFP_ATOMIC);
|
||||
if (!dma->sg_rx_p)
|
||||
return;
|
||||
|
||||
sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
|
||||
/* offset, length setting */
|
||||
sg = dma->sg_rx_p;
|
||||
@ -1068,6 +1071,9 @@ static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
|
||||
}
|
||||
|
||||
dma->sg_tx_p = kcalloc(num, sizeof(*dma->sg_tx_p), GFP_ATOMIC);
|
||||
if (!dma->sg_tx_p)
|
||||
return;
|
||||
|
||||
sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
|
||||
/* offset, length setting */
|
||||
sg = dma->sg_tx_p;
|
||||
|
Loading…
Reference in New Issue
Block a user