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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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PCI: dwc: Replace lower into upper case characters
Replace of all initial lowercase character in comments and debug messages to uppercase to maintain coherence. Fix messages coherence within the DesignWare driver. Fix code style on dw_pcie_irq_domain_free() function. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Joao Pinto <jpinto@synopsys.com>
This commit is contained in:
Gustavo Pimentel
Lorenzo Pieralisi
parent
2d27ae8998
commit
b4a8a51caf
@ -75,7 +75,7 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
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free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
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if (free_win >= ep->num_ib_windows) {
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dev_err(pci->dev, "no free inbound window\n");
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dev_err(pci->dev, "No free inbound window\n");
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return -EINVAL;
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}
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@ -100,7 +100,7 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
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free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
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if (free_win >= ep->num_ob_windows) {
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dev_err(pci->dev, "no free outbound window\n");
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dev_err(pci->dev, "No free outbound window\n");
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return -EINVAL;
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}
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@ -204,7 +204,7 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
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ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
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if (ret) {
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dev_err(pci->dev, "failed to enable address\n");
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dev_err(pci->dev, "Failed to enable address\n");
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return ret;
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}
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@ -348,21 +348,21 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
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ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
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if (ret < 0) {
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dev_err(dev, "unable to read *num-ib-windows* property\n");
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dev_err(dev, "Unable to read *num-ib-windows* property\n");
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return ret;
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}
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if (ep->num_ib_windows > MAX_IATU_IN) {
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dev_err(dev, "invalid *num-ib-windows*\n");
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dev_err(dev, "Invalid *num-ib-windows*\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
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if (ret < 0) {
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dev_err(dev, "unable to read *num-ob-windows* property\n");
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dev_err(dev, "Unable to read *num-ob-windows* property\n");
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return ret;
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}
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if (ep->num_ob_windows > MAX_IATU_OUT) {
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dev_err(dev, "invalid *num-ob-windows*\n");
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dev_err(dev, "Invalid *num-ob-windows*\n");
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return -EINVAL;
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}
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@ -389,7 +389,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
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epc = devm_pci_epc_create(dev, &epc_ops);
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if (IS_ERR(epc)) {
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dev_err(dev, "failed to create epc device\n");
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dev_err(dev, "Failed to create epc device\n");
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return PTR_ERR(epc);
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}
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@ -248,8 +248,10 @@ static void dw_pcie_irq_domain_free(struct irq_domain *domain,
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unsigned long flags;
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raw_spin_lock_irqsave(&pp->lock, flags);
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bitmap_release_region(pp->msi_irq_in_use, data->hwirq,
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order_base_2(nr_irqs));
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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}
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@ -266,7 +268,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
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pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
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&dw_pcie_msi_domain_ops, pp);
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if (!pp->irq_domain) {
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dev_err(pci->dev, "failed to create IRQ domain\n");
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dev_err(pci->dev, "Failed to create IRQ domain\n");
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return -ENOMEM;
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}
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@ -274,7 +276,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
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&dw_pcie_msi_domain_info,
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pp->irq_domain);
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if (!pp->msi_domain) {
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dev_err(pci->dev, "failed to create MSI domain\n");
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dev_err(pci->dev, "Failed to create MSI domain\n");
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irq_domain_remove(pp->irq_domain);
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return -ENOMEM;
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}
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@ -301,13 +303,13 @@ void dw_pcie_msi_init(struct pcie_port *pp)
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page = alloc_page(GFP_KERNEL);
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pp->msi_data = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
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if (dma_mapping_error(dev, pp->msi_data)) {
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dev_err(dev, "failed to map MSI data\n");
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dev_err(dev, "Failed to map MSI data\n");
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__free_page(page);
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return;
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}
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msi_target = (u64)pp->msi_data;
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/* program the msi_data */
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/* Program the msi_data */
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dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
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lower_32_bits(msi_target));
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dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
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@ -335,7 +337,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
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pp->cfg0_base = cfg_res->start;
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pp->cfg1_base = cfg_res->start + pp->cfg0_size;
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} else if (!pp->va_cfg0_base) {
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dev_err(dev, "missing *config* reg space\n");
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dev_err(dev, "Missing *config* reg space\n");
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}
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bridge = pci_alloc_host_bridge(0);
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@ -357,7 +359,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
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case IORESOURCE_IO:
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ret = pci_remap_iospace(win->res, pp->io_base);
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if (ret) {
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dev_warn(dev, "error %d: failed to map resource %pR\n",
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dev_warn(dev, "Error %d: failed to map resource %pR\n",
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ret, win->res);
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resource_list_destroy_entry(win);
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} else {
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@ -391,7 +393,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
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pp->cfg->start,
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resource_size(pp->cfg));
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if (!pci->dbi_base) {
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dev_err(dev, "error with ioremap\n");
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dev_err(dev, "Error with ioremap\n");
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ret = -ENOMEM;
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goto error;
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}
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@ -403,7 +405,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
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pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
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pp->cfg0_base, pp->cfg0_size);
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if (!pp->va_cfg0_base) {
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dev_err(dev, "error with ioremap in function\n");
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dev_err(dev, "Error with ioremap in function\n");
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ret = -ENOMEM;
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goto error;
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}
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@ -414,7 +416,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
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pp->cfg1_base,
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pp->cfg1_size);
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if (!pp->va_cfg1_base) {
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dev_err(dev, "error with ioremap\n");
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dev_err(dev, "Error with ioremap\n");
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ret = -ENOMEM;
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goto error;
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}
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@ -586,7 +588,7 @@ static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
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return 0;
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}
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/* access only one slot on each root port */
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/* Access only one slot on each root port */
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if (bus->number == pp->root_bus_nr && dev > 0)
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return 0;
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@ -652,11 +654,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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for (ctrl = 0; ctrl < num_ctrls; ctrl++)
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + (ctrl * 12), 4,
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&pp->irq_status[ctrl]);
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/* setup RC BARs */
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/* Setup RC BARs */
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
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/* setup interrupt pins */
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/* Setup interrupt pins */
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dw_pcie_dbi_ro_wr_en(pci);
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val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
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val &= 0xffff00ff;
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@ -664,13 +667,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
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dw_pcie_dbi_ro_wr_dis(pci);
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/* setup bus numbers */
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/* Setup bus numbers */
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val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
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val &= 0xff000000;
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val |= 0x00ff0100;
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dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
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/* setup command register */
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/* Setup command register */
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val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
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val &= 0xffff0000;
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val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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@ -683,7 +686,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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* we should not program the ATU here.
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*/
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if (!pp->ops->rd_other_conf) {
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/* get iATU unroll support */
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/* Get iATU unroll support */
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pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
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dev_dbg(pci->dev, "iATU unroll: %s\n",
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pci->iatu_unroll_enabled ? "enabled" : "disabled");
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@ -701,7 +704,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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/* Enable write permission for the DBI read-only register */
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dw_pcie_dbi_ro_wr_en(pci);
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/* program correct class for RC */
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/* Program correct class for RC */
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dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
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/* Better disable write permission right after the update */
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dw_pcie_dbi_ro_wr_dis(pci);
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@ -69,7 +69,7 @@ u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
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ret = dw_pcie_read(base + reg, size, &val);
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if (ret)
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dev_err(pci->dev, "read DBI address failed\n");
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dev_err(pci->dev, "Read DBI address failed\n");
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return val;
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}
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@ -86,7 +86,7 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
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ret = dw_pcie_write(base + reg, size, val);
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if (ret)
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dev_err(pci->dev, "write DBI address failed\n");
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dev_err(pci->dev, "Write DBI address failed\n");
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}
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static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
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@ -137,7 +137,7 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
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usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
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}
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dev_err(pci->dev, "outbound iATU is not being enabled\n");
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dev_err(pci->dev, "Outbound iATU is not being enabled\n");
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}
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void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
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@ -180,7 +180,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
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usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
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}
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dev_err(pci->dev, "outbound iATU is not being enabled\n");
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dev_err(pci->dev, "Outbound iATU is not being enabled\n");
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}
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static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
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@ -238,7 +238,7 @@ static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
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usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
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}
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dev_err(pci->dev, "inbound iATU is not being enabled\n");
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dev_err(pci->dev, "Inbound iATU is not being enabled\n");
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return -EBUSY;
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}
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@ -284,7 +284,7 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
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usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
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}
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dev_err(pci->dev, "inbound iATU is not being enabled\n");
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dev_err(pci->dev, "Inbound iATU is not being enabled\n");
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return -EBUSY;
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}
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@ -313,16 +313,16 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci)
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{
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int retries;
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/* check if the link is up or not */
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/* Check if the link is up or not */
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for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
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if (dw_pcie_link_up(pci)) {
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dev_info(pci->dev, "link up\n");
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dev_info(pci->dev, "Link up\n");
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return 0;
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}
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usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
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}
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dev_err(pci->dev, "phy link never came up\n");
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dev_err(pci->dev, "Phy link never came up\n");
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return -ETIMEDOUT;
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}
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@ -351,7 +351,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
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if (ret)
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lanes = 0;
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/* set the number of lanes */
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/* Set the number of lanes */
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val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
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val &= ~PORT_LINK_MODE_MASK;
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switch (lanes) {
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@ -373,7 +373,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
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}
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dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
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/* set link width speed control register */
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/* Set link width speed control register */
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val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
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val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
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switch (lanes) {
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