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x86/fpu/xstate: Add supervisor PASID state for ENQCMD
The ENQCMD instruction reads a PASID from the IA32_PASID MSR. The MSR is stored in the task's supervisor XSAVE* PASID state and is context-switched by XSAVES/XRSTORS. [ bp: Add (in-)definite articles and massage. ] Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> Co-developed-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Tony Luck <tony.luck@intel.com> Link: https://lkml.kernel.org/r/1600187413-163670-6-git-send-email-fenghua.yu@intel.com
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@ -114,7 +114,7 @@ enum xfeature {
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XFEATURE_Hi16_ZMM,
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XFEATURE_PT_UNIMPLEMENTED_SO_FAR,
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XFEATURE_PKRU,
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XFEATURE_RSRVD_COMP_10,
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XFEATURE_PASID,
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XFEATURE_RSRVD_COMP_11,
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XFEATURE_RSRVD_COMP_12,
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XFEATURE_RSRVD_COMP_13,
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@ -134,6 +134,7 @@ enum xfeature {
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#define XFEATURE_MASK_Hi16_ZMM (1 << XFEATURE_Hi16_ZMM)
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#define XFEATURE_MASK_PT (1 << XFEATURE_PT_UNIMPLEMENTED_SO_FAR)
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#define XFEATURE_MASK_PKRU (1 << XFEATURE_PKRU)
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#define XFEATURE_MASK_PASID (1 << XFEATURE_PASID)
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#define XFEATURE_MASK_LBR (1 << XFEATURE_LBR)
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#define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE)
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@ -256,6 +257,14 @@ struct arch_lbr_state {
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struct lbr_entry entries[];
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} __packed;
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/*
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* State component 10 is supervisor state used for context-switching the
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* PASID state.
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*/
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struct ia32_pasid_state {
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u64 pasid;
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} __packed;
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struct xstate_header {
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u64 xfeatures;
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u64 xcomp_bv;
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@ -35,7 +35,7 @@
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XFEATURE_MASK_BNDCSR)
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/* All currently supported supervisor features */
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#define XFEATURE_MASK_SUPERVISOR_SUPPORTED (0)
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#define XFEATURE_MASK_SUPERVISOR_SUPPORTED (XFEATURE_MASK_PASID)
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/*
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* A supervisor state component may not always contain valuable information,
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@ -37,6 +37,7 @@ static const char *xfeature_names[] =
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"AVX-512 ZMM_Hi256" ,
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"Processor Trace (unused)" ,
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"Protection Keys User registers",
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"PASID state",
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"unknown xstate feature" ,
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};
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@ -51,6 +52,7 @@ static short xsave_cpuid_features[] __initdata = {
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X86_FEATURE_AVX512F,
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X86_FEATURE_INTEL_PT,
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X86_FEATURE_PKU,
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X86_FEATURE_ENQCMD,
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};
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/*
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@ -318,6 +320,7 @@ static void __init print_xstate_features(void)
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print_xstate_feature(XFEATURE_MASK_ZMM_Hi256);
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print_xstate_feature(XFEATURE_MASK_Hi16_ZMM);
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print_xstate_feature(XFEATURE_MASK_PKRU);
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print_xstate_feature(XFEATURE_MASK_PASID);
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}
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/*
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@ -592,6 +595,7 @@ static void check_xstate_against_struct(int nr)
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XCHECK_SZ(sz, nr, XFEATURE_ZMM_Hi256, struct avx_512_zmm_uppers_state);
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XCHECK_SZ(sz, nr, XFEATURE_Hi16_ZMM, struct avx_512_hi16_state);
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XCHECK_SZ(sz, nr, XFEATURE_PKRU, struct pkru_state);
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XCHECK_SZ(sz, nr, XFEATURE_PASID, struct ia32_pasid_state);
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/*
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* Make *SURE* to add any feature numbers in below if
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@ -601,7 +605,7 @@ static void check_xstate_against_struct(int nr)
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if ((nr < XFEATURE_YMM) ||
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(nr >= XFEATURE_MAX) ||
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(nr == XFEATURE_PT_UNIMPLEMENTED_SO_FAR) ||
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((nr >= XFEATURE_RSRVD_COMP_10) && (nr <= XFEATURE_LBR))) {
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((nr >= XFEATURE_RSRVD_COMP_11) && (nr <= XFEATURE_LBR))) {
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WARN_ONCE(1, "no structure for xstate: %d\n", nr);
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XSTATE_WARN_ON(1);
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}
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