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x86, amd: Enable L3 cache index disable on family 0x15

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AMD family 0x15 CPUs support L3 cache index disable, so enable
it on them.

Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com>
Cc: <andreas.herrmann3@amd.com>
LKML-Reference: <1295881543-572552-3-git-send-email-hans.rosenfeld@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Hans Rosenfeld 2011-01-24 16:05:41 +01:00 committed by Ingo Molnar
parent d518573de6
commit b453de02b7
1 changed files with 3 additions and 0 deletions
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3
arch/x86/kernel/amd_nb.c
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@ -85,6 +85,9 @@ int amd_cache_northbridges(void)
boot_cpu_data.x86_mask >= 0x1)) boot_cpu_data.x86_mask >= 0x1))
amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
if (boot_cpu_data.x86 == 0x15)
amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(amd_cache_northbridges); EXPORT_SYMBOL_GPL(amd_cache_northbridges);