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clk: ti: add support for clock latching to divider clocks
Latching the clock settings is needed with certain clocks, where the setting is "cached" in HW before doing the actual re-programming of the clock source. This patch adds support for clock latching to the divider clock. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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@ -22,6 +22,7 @@ struct clk_omap_divider {
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u8 shift;
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u8 width;
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u8 flags;
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s8 latch;
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const struct clk_div_table *table;
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};
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@ -263,6 +263,8 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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val |= value << divider->shift;
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ti_clk_ll_ops->clk_writel(val, ÷r->reg);
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ti_clk_latch(÷r->reg, divider->latch);
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return 0;
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}
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@ -276,7 +278,8 @@ static struct clk *_register_divider(struct device *dev, const char *name,
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const char *parent_name,
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unsigned long flags,
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struct clk_omap_reg *reg,
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u8 shift, u8 width, u8 clk_divider_flags,
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u8 shift, u8 width, s8 latch,
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u8 clk_divider_flags,
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const struct clk_div_table *table)
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{
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struct clk_omap_divider *div;
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@ -305,6 +308,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,
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memcpy(&div->reg, reg, sizeof(*reg));
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div->shift = shift;
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div->width = width;
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div->latch = latch;
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div->flags = clk_divider_flags;
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div->hw.init = &init;
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div->table = table;
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@ -420,6 +424,7 @@ struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
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div->table = _get_div_table_from_setup(setup, &div->width);
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div->shift = setup->bit_shift;
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div->latch = -EINVAL;
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return &div->hw;
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}
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@ -452,7 +457,7 @@ struct clk *ti_clk_register_divider(struct ti_clk *setup)
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clk = _register_divider(NULL, setup->name, div->parent,
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flags, ®, div->bit_shift,
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width, div_flags, table);
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width, -EINVAL, div_flags, table);
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if (IS_ERR(clk))
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kfree(table);
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@ -556,7 +561,7 @@ static int _get_divider_width(struct device_node *node,
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static int __init ti_clk_divider_populate(struct device_node *node,
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struct clk_omap_reg *reg, const struct clk_div_table **table,
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u32 *flags, u8 *div_flags, u8 *width, u8 *shift)
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u32 *flags, u8 *div_flags, u8 *width, u8 *shift, s8 *latch)
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{
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u32 val;
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int ret;
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@ -570,6 +575,13 @@ static int __init ti_clk_divider_populate(struct device_node *node,
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else
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*shift = 0;
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if (latch) {
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if (!of_property_read_u32(node, "ti,latch-bit", &val))
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*latch = val;
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else
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*latch = -EINVAL;
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}
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*flags = 0;
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*div_flags = 0;
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@ -606,17 +618,18 @@ static void __init of_ti_divider_clk_setup(struct device_node *node)
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u8 clk_divider_flags = 0;
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u8 width = 0;
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u8 shift = 0;
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s8 latch = -EINVAL;
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const struct clk_div_table *table = NULL;
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u32 flags = 0;
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parent_name = of_clk_get_parent_name(node, 0);
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if (ti_clk_divider_populate(node, ®, &table, &flags,
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&clk_divider_flags, &width, &shift))
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&clk_divider_flags, &width, &shift, &latch))
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goto cleanup;
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clk = _register_divider(NULL, node->name, parent_name, flags, ®,
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shift, width, clk_divider_flags, table);
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shift, width, latch, clk_divider_flags, table);
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if (!IS_ERR(clk)) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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@ -639,7 +652,8 @@ static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
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return;
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if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
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&div->flags, &div->width, &div->shift) < 0)
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&div->flags, &div->width, &div->shift,
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NULL) < 0)
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goto cleanup;
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if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
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