AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-11-25 18:50:55 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

PCI: Add ACS quirk for all Cavium devices

Browse Source 
Cavium devices matching this quirk do not perform peer-to-peer with other
functions, allowing masking out these bits as if they were unimplemented in
the ACS capability.

Signed-off-by: Manish Jaggi <mjaggi@caviumnetworks.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Tirumalesh Chalamarla <tchalamarla@cavium.com>
This commit is contained in:
Manish Jaggi 2016-01-30 01:33:58 +05:30 committed by Bjorn Helgaas
parent 92e963f50f
commit b404bcfbf0
1 changed files with 15 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/pci/quirks.c
View File

@ -3832,6 +3832,19 @@ static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
#endif
}
static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
{
/*
* Cavium devices matching this quirk do not perform peer-to-peer
* with other functions, allowing masking out these bits as if they
* were unimplemented in the ACS capability.
*/
acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
return acs_flags ? 0 : 1;
}
/*
* Many Intel PCH root ports do provide ACS-like features to disable peer
* transactions and validate bus numbers in requests, but do not provide an
@ -3984,6 +3997,8 @@ static const struct pci_dev_acs_enabled {
{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
{ 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
/* Cavium ThunderX */
{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
{ 0 }
};