mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-02-24 08:56:20 +07:00
mt76x0: remove eeprom dependency from mt76x0_set_tx_power_per_rate
In order to unify eeprom parsing between mt76x0 and mt76x2 drivers, remove eeprom pointer dependency from mt76x0_set_tx_power_per_rate. Moreover use mt76_rate_power to store power vs rate calibration data. Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@redhat.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
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0050507c77
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b37bbc8c82
@ -118,19 +118,6 @@ mt76x0_eeprom_param_read(struct seq_file *file, void *data)
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for (i = 0; i < 58; i++)
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seq_printf(file, "\t%d chan:%d pwr:%d\n", i, i,
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dev->ee->tx_pwr_per_chan[i]);
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seq_puts(file, "Per rate power 2GHz:\n");
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for (i = 0; i < 5; i++)
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seq_printf(file, "\t %d bw20:%d bw40:%d\n",
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i, dev->ee->tx_pwr_cfg_2g[i][0],
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dev->ee->tx_pwr_cfg_5g[i][1]);
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seq_puts(file, "Per rate power 5GHz:\n");
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for (i = 0; i < 5; i++)
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seq_printf(file, "\t %d bw20:%d bw40:%d\n",
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i, dev->ee->tx_pwr_cfg_5g[i][0],
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dev->ee->tx_pwr_cfg_5g[i][1]);
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return 0;
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}
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@ -147,6 +134,23 @@ static const struct file_operations fops_eeprom_param = {
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.release = single_release,
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};
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static int mt76x0_read_txpower(struct seq_file *file, void *data)
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{
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struct mt76x0_dev *dev = dev_get_drvdata(file->private);
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mt76_seq_puts_array(file, "CCK", dev->mt76.rate_power.cck,
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ARRAY_SIZE(dev->mt76.rate_power.cck));
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mt76_seq_puts_array(file, "OFDM", dev->mt76.rate_power.ofdm,
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ARRAY_SIZE(dev->mt76.rate_power.ofdm));
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mt76_seq_puts_array(file, "STBC", dev->mt76.rate_power.stbc,
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ARRAY_SIZE(dev->mt76.rate_power.stbc));
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mt76_seq_puts_array(file, "HT", dev->mt76.rate_power.ht,
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ARRAY_SIZE(dev->mt76.rate_power.ht));
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mt76_seq_puts_array(file, "VHT", dev->mt76.rate_power.vht,
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ARRAY_SIZE(dev->mt76.rate_power.vht));
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return 0;
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}
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void mt76x0_init_debugfs(struct mt76x0_dev *dev)
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{
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struct dentry *dir;
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@ -161,4 +165,6 @@ void mt76x0_init_debugfs(struct mt76x0_dev *dev)
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debugfs_create_file("ampdu_stat", S_IRUSR, dir, dev, &fops_ampdu_stat);
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debugfs_create_file("eeprom_param", S_IRUSR, dir, dev,
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&fops_eeprom_param);
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debugfs_create_devm_seqfile(dev->mt76.dev, "txpower", dir,
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mt76x0_read_txpower);
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}
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@ -20,6 +20,7 @@
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#include <asm/unaligned.h>
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#include "mt76x0.h"
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#include "eeprom.h"
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#include "../mt76x02_phy.h"
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#define MT_MAP_READS DIV_ROUND_UP(MT_EFUSE_USAGE_MAP_SIZE, 16)
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static int
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@ -125,82 +126,88 @@ void mt76x0_read_rx_gain(struct mt76x0_dev *dev)
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}
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}
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static u32
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calc_bw40_power_rate(u32 value, int delta)
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static s8 mt76x0_get_delta(struct mt76_dev *dev)
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{
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u32 ret = 0;
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int i, tmp;
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struct cfg80211_chan_def *chandef = &dev->chandef;
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u8 val;
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for (i = 0; i < 4; i++) {
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tmp = s6_to_int((value >> i*8) & 0xff) + delta;
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ret |= (u32)(int_to_s6(tmp)) << i*8;
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}
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return ret;
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}
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static s8
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get_delta(u8 val)
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{
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s8 ret;
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if (!mt76x02_field_valid(val) || !(val & BIT(7)))
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if (mt76x02_tssi_enabled(dev))
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return 0;
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ret = val & 0x1f;
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if (ret > 8)
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ret = 8;
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if (val & BIT(6))
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ret = -ret;
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if (chandef->width == NL80211_CHAN_WIDTH_80) {
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val = mt76x02_eeprom_get(dev, MT_EE_5G_TARGET_POWER) >> 8;
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} else if (chandef->width == NL80211_CHAN_WIDTH_40) {
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u16 data;
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return ret;
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}
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static void
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mt76x0_set_tx_power_per_rate(struct mt76x0_dev *dev, u8 *eeprom)
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{
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s8 bw40_delta_2g, bw40_delta_5g;
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u32 val;
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int i;
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bw40_delta_2g = get_delta(eeprom[MT_EE_TX_POWER_DELTA_BW40]);
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bw40_delta_5g = get_delta(eeprom[MT_EE_TX_POWER_DELTA_BW40 + 1]);
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for (i = 0; i < 5; i++) {
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val = get_unaligned_le32(eeprom + MT_EE_TX_POWER_BYRATE(i));
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/* Skip last 16 bits. */
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if (i == 4)
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val &= 0x0000ffff;
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dev->ee->tx_pwr_cfg_2g[i][0] = val;
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dev->ee->tx_pwr_cfg_2g[i][1] = calc_bw40_power_rate(val, bw40_delta_2g);
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data = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW40);
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if (chandef->chan->band == NL80211_BAND_5GHZ)
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val = data >> 8;
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else
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val = data;
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} else {
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return 0;
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}
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/* Reading per rate tx power for 5 GHz band is a bit more complex. Note
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* we mix 16 bit and 32 bit reads and sometimes do shifts.
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*/
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val = get_unaligned_le16(eeprom + 0x120);
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val <<= 16;
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dev->ee->tx_pwr_cfg_5g[0][0] = val;
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dev->ee->tx_pwr_cfg_5g[0][1] = calc_bw40_power_rate(val, bw40_delta_5g);
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return mt76x02_rate_power_val(val);
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}
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val = get_unaligned_le32(eeprom + 0x122);
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dev->ee->tx_pwr_cfg_5g[1][0] = val;
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dev->ee->tx_pwr_cfg_5g[1][1] = calc_bw40_power_rate(val, bw40_delta_5g);
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void mt76x0_get_tx_power_per_rate(struct mt76x0_dev *dev)
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{
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struct ieee80211_channel *chan = dev->mt76.chandef.chan;
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bool is_2ghz = chan->band == NL80211_BAND_2GHZ;
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struct mt76_rate_power *t = &dev->mt76.rate_power;
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s8 delta = mt76x0_get_delta(&dev->mt76);
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u16 val, addr;
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val = get_unaligned_le16(eeprom + 0x126);
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dev->ee->tx_pwr_cfg_5g[2][0] = val;
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dev->ee->tx_pwr_cfg_5g[2][1] = calc_bw40_power_rate(val, bw40_delta_5g);
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memset(t, 0, sizeof(*t));
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val = get_unaligned_le16(eeprom + 0xec);
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val <<= 16;
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dev->ee->tx_pwr_cfg_5g[3][0] = val;
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dev->ee->tx_pwr_cfg_5g[3][1] = calc_bw40_power_rate(val, bw40_delta_5g);
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/* cck 1M, 2M, 5.5M, 11M */
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val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_BYRATE_BASE);
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t->cck[0] = t->cck[1] = s6_to_s8(val);
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t->cck[2] = t->cck[3] = s6_to_s8(val >> 8);
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val = get_unaligned_le16(eeprom + 0xee);
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dev->ee->tx_pwr_cfg_5g[4][0] = val;
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dev->ee->tx_pwr_cfg_5g[4][1] = calc_bw40_power_rate(val, bw40_delta_5g);
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/* ofdm 6M, 9M, 12M, 18M */
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addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 2 : 0x120;
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val = mt76x02_eeprom_get(&dev->mt76, addr);
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t->ofdm[0] = t->ofdm[1] = s6_to_s8(val);
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t->ofdm[2] = t->ofdm[3] = s6_to_s8(val >> 8);
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/* ofdm 24M, 36M, 48M, 54M */
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addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 4 : 0x122;
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val = mt76x02_eeprom_get(&dev->mt76, addr);
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t->ofdm[4] = t->ofdm[5] = s6_to_s8(val);
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t->ofdm[6] = t->ofdm[7] = s6_to_s8(val >> 8);
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/* ht-vht mcs 1ss 0, 1, 2, 3 */
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addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 6 : 0x124;
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val = mt76x02_eeprom_get(&dev->mt76, addr);
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t->ht[0] = t->ht[1] = t->vht[0] = t->vht[1] = s6_to_s8(val);
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t->ht[2] = t->ht[3] = t->vht[2] = t->vht[3] = s6_to_s8(val >> 8);
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/* ht-vht mcs 1ss 4, 5, 6 */
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addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 8 : 0x126;
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val = mt76x02_eeprom_get(&dev->mt76, addr);
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t->ht[4] = t->ht[5] = t->vht[4] = t->vht[5] = s6_to_s8(val);
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t->ht[6] = t->vht[6] = s6_to_s8(val >> 8);
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/* ht-vht mcs 1ss 0, 1, 2, 3 stbc */
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addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 14 : 0xec;
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val = mt76x02_eeprom_get(&dev->mt76, addr);
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t->stbc[0] = t->stbc[1] = s6_to_s8(val);
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t->stbc[2] = t->stbc[3] = s6_to_s8(val >> 8);
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/* ht-vht mcs 1ss 4, 5, 6 stbc */
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addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 16 : 0xee;
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val = mt76x02_eeprom_get(&dev->mt76, addr);
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t->stbc[4] = t->stbc[5] = s6_to_s8(val);
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t->stbc[6] = t->stbc[7] = s6_to_s8(val >> 8);
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/* vht mcs 8, 9 5GHz */
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val = mt76x02_eeprom_get(&dev->mt76, 0x132);
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t->vht[7] = s6_to_s8(val);
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t->vht[8] = s6_to_s8(val >> 8);
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mt76x02_add_rate_power_offset(t, delta);
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}
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static void
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@ -271,7 +278,6 @@ mt76x0_eeprom_init(struct mt76x0_dev *dev)
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mt76x0_set_temp_offset(dev);
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dev->chainmask = 0x0101;
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mt76x0_set_tx_power_per_rate(dev, eeprom);
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mt76x0_set_tx_power_per_chan(dev, eeprom);
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out:
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@ -37,41 +37,21 @@ struct mt76x0_caldata {
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};
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struct mt76x0_eeprom_params {
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/* TX_PWR_CFG_* values from EEPROM for 20 and 40 Mhz bandwidths. */
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u32 tx_pwr_cfg_2g[5][2];
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u32 tx_pwr_cfg_5g[5][2];
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u8 tx_pwr_per_chan[58];
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};
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int mt76x0_eeprom_init(struct mt76x0_dev *dev);
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void mt76x0_read_rx_gain(struct mt76x0_dev *dev);
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void mt76x0_get_tx_power_per_rate(struct mt76x0_dev *dev);
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static inline u32 s6_validate(u32 reg)
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static inline s8 s6_to_s8(u32 val)
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{
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WARN_ON(reg & ~GENMASK(5, 0));
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return reg & GENMASK(5, 0);
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}
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s8 ret = val & GENMASK(5, 0);
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static inline int s6_to_int(u32 reg)
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{
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int s6;
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s6 = s6_validate(reg);
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if (s6 & BIT(5))
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s6 -= BIT(6);
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return s6;
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}
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static inline u32 int_to_s6(int val)
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{
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if (val < -0x20)
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return 0x20;
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if (val > 0x1f)
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return 0x1f;
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return val & 0x3f;
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if (ret & BIT(5))
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ret -= BIT(6);
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return ret;
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}
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#endif
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@ -641,6 +641,7 @@ __mt76x0_phy_set_channel(struct mt76x0_dev *dev,
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freq1 = chandef->center_freq1;
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channel = chandef->chan->hw_value;
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rf_bw_band = (channel <= 14) ? RF_G_BAND : RF_A_BAND;
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dev->mt76.chandef = *chandef;
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switch (chandef->width) {
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case NL80211_CHAN_WIDTH_40:
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@ -678,6 +679,7 @@ __mt76x0_phy_set_channel(struct mt76x0_dev *dev,
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mt76x0_phy_set_band(dev, chandef->chan->band);
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mt76x0_phy_set_chan_rf_params(dev, channel, rf_bw_band);
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mt76x0_get_tx_power_per_rate(dev);
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mt76x0_read_rx_gain(dev);
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/* set Japan Tx filter at channel 14 */
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@ -699,7 +701,6 @@ __mt76x0_phy_set_channel(struct mt76x0_dev *dev,
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mt76x0_phy_set_chan_pwr(dev, channel);
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dev->mt76.chandef = *chandef;
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return 0;
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}
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@ -74,6 +74,7 @@ enum mt76x02_eeprom_field {
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MT_EE_2G_TARGET_POWER = 0x0d0,
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MT_EE_TEMP_OFFSET = 0x0d1,
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MT_EE_5G_TARGET_POWER = 0x0d2,
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MT_EE_TSSI_BOUND1 = 0x0d4,
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MT_EE_TSSI_BOUND2 = 0x0d6,
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MT_EE_TSSI_BOUND3 = 0x0d8,
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@ -121,9 +122,6 @@ enum mt76x02_eeprom_field {
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#define MT_EE_NIC_CONF_2_TEMP_DISABLE BIT(11)
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#define MT_EE_NIC_CONF_2_COEX_METHOD GENMASK(15, 13)
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#define MT_EE_TX_POWER_BYRATE(x) (MT_EE_TX_POWER_BYRATE_BASE + \
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(x) * 4)
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#define MT_EFUSE_USAGE_MAP_SIZE (MT_EE_USAGE_MAP_END - \
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MT_EE_USAGE_MAP_START + 1)
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