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sh_eth: Fix access to TRSCER register
TRSCER register is configured differently by SoCs. TRSCER of R-Car Gen2 is RINT8 bit only valid, other bits are reserved bits. This removes access to TRSCER register reserve bit by adding variable trscer_err_mask to sh_eth_cpu_data structure, set the register information to each SoCs. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -538,6 +538,8 @@ static struct sh_eth_cpu_data sh7724_data = {
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EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
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EESR_ECI,
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.trscer_err_mask = DESC_I_RINT8,
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.apr = 1,
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.mpr = 1,
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.tpauser = 1,
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@ -858,6 +860,9 @@ static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
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if (!cd->eesr_err_check)
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cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
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if (!cd->trscer_err_mask)
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cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
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}
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static int sh_eth_check_reset(struct net_device *ndev)
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@ -1296,7 +1301,7 @@ static int sh_eth_dev_init(struct net_device *ndev, bool start)
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/* Frame recv control (enable multiple-packets per rx irq) */
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sh_eth_write(ndev, RMCR_RNC, RMCR);
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sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
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sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
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if (mdp->cd->bculr)
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sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
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@ -369,6 +369,8 @@ enum DESC_I_BIT {
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DESC_I_RINT1 = 0x0001,
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};
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#define DEFAULT_TRSCER_ERR_MASK (DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2)
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/* RPADIR */
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enum RPADIR_BIT {
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RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
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@ -470,6 +472,9 @@ struct sh_eth_cpu_data {
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unsigned long tx_check;
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unsigned long eesr_err_check;
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/* Error mask */
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unsigned long trscer_err_mask;
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/* hardware features */
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unsigned long irq_flags; /* IRQ configuration flags */
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unsigned no_psr:1; /* EtherC DO NOT have PSR */
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