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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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mtd: rawnand: davinci: convert driver to nand_scan()
Two helpers have been added to the core to do all kind of controller side configuration/initialization between the detection phase and the final NAND scan. Implement these hooks so that we can convert the driver to just use nand_scan() instead of the nand_scan_ident() + nand_scan_tail() pair. Also change the unused "struct device *dev" parameter of the driver structure into a platform device to reuse it in the ->attach_chip() hook. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
This commit is contained in:
Miquel Raynal
parent
c1070db383
commit
b2342c1c80
@ -53,7 +53,7 @@
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struct davinci_nand_info {
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struct nand_chip chip;
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struct device *dev;
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struct platform_device *pdev;
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bool is_readmode;
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@ -605,6 +605,104 @@ static struct davinci_nand_pdata
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}
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#endif
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static int davinci_nand_attach_chip(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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struct davinci_nand_pdata *pdata = nand_davinci_get_pdata(info->pdev);
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int ret = 0;
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if (IS_ERR(pdata))
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return PTR_ERR(pdata);
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switch (info->chip.ecc.mode) {
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case NAND_ECC_NONE:
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pdata->ecc_bits = 0;
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break;
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case NAND_ECC_SOFT:
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pdata->ecc_bits = 0;
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/*
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* This driver expects Hamming based ECC when ecc_mode is set
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* to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
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* avoid adding an extra ->ecc_algo field to
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* davinci_nand_pdata.
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*/
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info->chip.ecc.algo = NAND_ECC_HAMMING;
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break;
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case NAND_ECC_HW:
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if (pdata->ecc_bits == 4) {
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/*
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* No sanity checks: CPUs must support this,
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* and the chips may not use NAND_BUSWIDTH_16.
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*/
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/* No sharing 4-bit hardware between chipselects yet */
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spin_lock_irq(&davinci_nand_lock);
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if (ecc4_busy)
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ret = -EBUSY;
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else
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ecc4_busy = true;
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spin_unlock_irq(&davinci_nand_lock);
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if (ret == -EBUSY)
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return ret;
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info->chip.ecc.calculate = nand_davinci_calculate_4bit;
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info->chip.ecc.correct = nand_davinci_correct_4bit;
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info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
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info->chip.ecc.bytes = 10;
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info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
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info->chip.ecc.algo = NAND_ECC_BCH;
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} else {
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/* 1bit ecc hamming */
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info->chip.ecc.calculate = nand_davinci_calculate_1bit;
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info->chip.ecc.correct = nand_davinci_correct_1bit;
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info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
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info->chip.ecc.bytes = 3;
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info->chip.ecc.algo = NAND_ECC_HAMMING;
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}
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info->chip.ecc.size = 512;
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info->chip.ecc.strength = pdata->ecc_bits;
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break;
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default:
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return -EINVAL;
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}
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/*
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* Update ECC layout if needed ... for 1-bit HW ECC, the default
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* is OK, but it allocates 6 bytes when only 3 are needed (for
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* each 512 bytes). For the 4-bit HW ECC, that default is not
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* usable: 10 bytes are needed, not 6.
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*/
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if (pdata->ecc_bits == 4) {
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int chunks = mtd->writesize / 512;
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if (!chunks || mtd->oobsize < 16) {
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dev_dbg(&info->pdev->dev, "too small\n");
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return -EINVAL;
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}
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/* For small page chips, preserve the manufacturer's
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* badblock marking data ... and make sure a flash BBT
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* table marker fits in the free bytes.
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*/
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if (chunks == 1) {
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mtd_set_ooblayout(mtd, &hwecc4_small_ooblayout_ops);
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} else if (chunks == 4 || chunks == 8) {
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mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
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info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
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} else {
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return -EIO;
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}
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}
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return ret;
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}
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static const struct nand_controller_ops davinci_nand_controller_ops = {
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.attach_chip = davinci_nand_attach_chip,
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};
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static int nand_davinci_probe(struct platform_device *pdev)
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{
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struct davinci_nand_pdata *pdata;
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@ -658,7 +756,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
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return -EADDRNOTAVAIL;
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}
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info->dev = &pdev->dev;
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info->pdev = pdev;
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info->base = base;
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info->vaddr = vaddr;
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@ -708,97 +806,13 @@ static int nand_davinci_probe(struct platform_device *pdev)
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spin_unlock_irq(&davinci_nand_lock);
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/* Scan to find existence of the device(s) */
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ret = nand_scan_ident(mtd, pdata->mask_chipsel ? 2 : 1, NULL);
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info->chip.dummy_controller.ops = &davinci_nand_controller_ops;
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ret = nand_scan(mtd, pdata->mask_chipsel ? 2 : 1);
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if (ret < 0) {
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dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
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return ret;
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}
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switch (info->chip.ecc.mode) {
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case NAND_ECC_NONE:
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pdata->ecc_bits = 0;
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break;
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case NAND_ECC_SOFT:
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pdata->ecc_bits = 0;
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/*
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* This driver expects Hamming based ECC when ecc_mode is set
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* to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
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* avoid adding an extra ->ecc_algo field to
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* davinci_nand_pdata.
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*/
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info->chip.ecc.algo = NAND_ECC_HAMMING;
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break;
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case NAND_ECC_HW:
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if (pdata->ecc_bits == 4) {
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/* No sanity checks: CPUs must support this,
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* and the chips may not use NAND_BUSWIDTH_16.
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*/
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/* No sharing 4-bit hardware between chipselects yet */
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spin_lock_irq(&davinci_nand_lock);
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if (ecc4_busy)
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ret = -EBUSY;
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else
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ecc4_busy = true;
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spin_unlock_irq(&davinci_nand_lock);
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if (ret == -EBUSY)
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return ret;
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info->chip.ecc.calculate = nand_davinci_calculate_4bit;
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info->chip.ecc.correct = nand_davinci_correct_4bit;
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info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
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info->chip.ecc.bytes = 10;
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info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
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info->chip.ecc.algo = NAND_ECC_BCH;
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} else {
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/* 1bit ecc hamming */
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info->chip.ecc.calculate = nand_davinci_calculate_1bit;
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info->chip.ecc.correct = nand_davinci_correct_1bit;
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info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
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info->chip.ecc.bytes = 3;
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info->chip.ecc.algo = NAND_ECC_HAMMING;
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}
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info->chip.ecc.size = 512;
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info->chip.ecc.strength = pdata->ecc_bits;
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break;
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default:
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return -EINVAL;
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}
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/* Update ECC layout if needed ... for 1-bit HW ECC, the default
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* is OK, but it allocates 6 bytes when only 3 are needed (for
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* each 512 bytes). For the 4-bit HW ECC, that default is not
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* usable: 10 bytes are needed, not 6.
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*/
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if (pdata->ecc_bits == 4) {
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int chunks = mtd->writesize / 512;
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if (!chunks || mtd->oobsize < 16) {
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dev_dbg(&pdev->dev, "too small\n");
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ret = -EINVAL;
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goto err;
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}
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/* For small page chips, preserve the manufacturer's
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* badblock marking data ... and make sure a flash BBT
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* table marker fits in the free bytes.
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*/
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if (chunks == 1) {
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mtd_set_ooblayout(mtd, &hwecc4_small_ooblayout_ops);
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} else if (chunks == 4 || chunks == 8) {
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mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
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info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
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} else {
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ret = -EIO;
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goto err;
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}
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}
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ret = nand_scan_tail(mtd);
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if (ret < 0)
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goto err;
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if (pdata->parts)
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ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
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else
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@ -815,11 +829,6 @@ static int nand_davinci_probe(struct platform_device *pdev)
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err_cleanup_nand:
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nand_cleanup(&info->chip);
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err:
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spin_lock_irq(&davinci_nand_lock);
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if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
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ecc4_busy = false;
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spin_unlock_irq(&davinci_nand_lock);
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return ret;
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}
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