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edac: add DDR3 memory type for MPC85xx EDAC

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Since some new MPC85xx SOCs support DDR3 memory now, so add DDR3 memory
type for MPC85xx EDAC.

Signed-off-by: Yang Shi <yang.shi@windriver.com>
Cc: Doug Thompson <norsk5@yahoo.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Yang Shi 2009-06-30 11:41:22 -07:00 committed by Linus Torvalds
parent c4285b47b0
commit b1cfebc923
4 changed files with 14 additions and 1 deletions
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4
drivers/edac/edac_core.h
View File

@ -150,6 +150,8 @@ enum mem_type {
MEM_FB_DDR2, /* fully buffered DDR2 */ MEM_FB_DDR2, /* fully buffered DDR2 */
MEM_RDDR2, /* Registered DDR2 RAM */ MEM_RDDR2, /* Registered DDR2 RAM */
MEM_XDR, /* Rambus XDR */ MEM_XDR, /* Rambus XDR */
MEM_DDR3, /* DDR3 RAM */
MEM_RDDR3, /* Registered DDR3 RAM */
}; };
#define MEM_FLAG_EMPTY BIT(MEM_EMPTY) #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
@ -167,6 +169,8 @@ enum mem_type {
#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
#define MEM_FLAG_XDR BIT(MEM_XDR) #define MEM_FLAG_XDR BIT(MEM_XDR)
#define MEM_FLAG_DDR3 BIT(MEM_DDR3)
#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
/* chipset Error Detection and Correction capabilities and mode */ /* chipset Error Detection and Correction capabilities and mode */
enum edac_type { enum edac_type {

4
drivers/edac/edac_mc_sysfs.c
View File

@ -94,7 +94,9 @@ static const char *mem_types[] = {
[MEM_DDR2] = "Unbuffered-DDR2", [MEM_DDR2] = "Unbuffered-DDR2",
[MEM_FB_DDR2] = "FullyBuffered-DDR2", [MEM_FB_DDR2] = "FullyBuffered-DDR2",
[MEM_RDDR2] = "Registered-DDR2", [MEM_RDDR2] = "Registered-DDR2",
[MEM_XDR] = "XDR" [MEM_XDR] = "XDR",
[MEM_DDR3] = "Unbuffered-DDR3",
[MEM_RDDR3] = "Registered-DDR3"
}; };
static const char *dev_types[] = { static const char *dev_types[] = {

6
drivers/edac/mpc85xx_edac.c
View File

@ -757,6 +757,9 @@ static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
case DSC_SDTYPE_DDR2: case DSC_SDTYPE_DDR2:
mtype = MEM_RDDR2; mtype = MEM_RDDR2;
break; break;
case DSC_SDTYPE_DDR3:
mtype = MEM_RDDR3;
break;
default: default:
mtype = MEM_UNKNOWN; mtype = MEM_UNKNOWN;
break; break;
@ -769,6 +772,9 @@ static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
case DSC_SDTYPE_DDR2: case DSC_SDTYPE_DDR2:
mtype = MEM_DDR2; mtype = MEM_DDR2;
break; break;
case DSC_SDTYPE_DDR3:
mtype = MEM_DDR3;
break;
default: default:
mtype = MEM_UNKNOWN; mtype = MEM_UNKNOWN;
break; break;

1
drivers/edac/mpc85xx_edac.h
View File

@ -53,6 +53,7 @@
#define DSC_SDTYPE_DDR 0x02000000 #define DSC_SDTYPE_DDR 0x02000000
#define DSC_SDTYPE_DDR2 0x03000000 #define DSC_SDTYPE_DDR2 0x03000000
#define DSC_SDTYPE_DDR3 0x07000000
#define DSC_X32_EN 0x00000020 #define DSC_X32_EN 0x00000020
/* Err_Int_En */ /* Err_Int_En */