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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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rtlwifi: rtl8192ee: Move driver from staging to the regular tree
This driver was entered into staging a few cycles ago because there was not time to integrate the Realtek version into the support routines in the kernel. Now that there is an effort to converg the code base from Linux and the Realtek repo, it is time to move this driver. In addition, all the updates included in the 06/28/2014 version of the Realtek drivers are included here. With this change, it will be necessary to delete the staging driver. That will be handled in a separate patch. As it impacts the staging tree, such a patch is sent to a different destination. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Larry Finger
John W. Linville
parent
7fe3b3abb5
commit
b1a3bfc97c
@ -5,7 +5,8 @@ menuconfig RTL_CARDS
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---help---
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This option will enable support for the Realtek mac80211-based
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wireless drivers. Drivers rtl8192ce, rtl8192cu, rtl8192se, rtl8192de,
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rtl8723ae, rtl8723be, rtl8188ee, and rtl8821ae share some common code.
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rtl8723ae, rtl8723be, rtl8188ee, rtl8192ee, and rtl8821ae share
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some common code.
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if RTL_CARDS
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@ -80,6 +81,17 @@ config RTL8188EE
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If you choose to build it as a module, it will be called rtl8188ee
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config RTL8192EE
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tristate "Realtek RTL8192EE Wireless Network Adapter"
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depends on PCI
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select RTLWIFI
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select RTLWIFI_PCI
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---help---
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This is the driver for Realtek RTL8192EE 802.11n PCIe
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wireless network adapters.
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If you choose to build it as a module, it will be called rtl8192ee
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config RTL8821AE
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tristate "Realtek RTL8821AE/RTL8812AE Wireless Network Adapter"
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depends on PCI
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@ -29,5 +29,6 @@ obj-$(CONFIG_RTL8188EE) += rtl8188ee/
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obj-$(CONFIG_RTLBTCOEXIST) += btcoexist/
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obj-$(CONFIG_RTL8723_COMMON) += rtl8723com/
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obj-$(CONFIG_RTL8821AE) += rtl8821ae/
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obj-$(CONFIG_RTL8192EE) += rtl8192ee/
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ccflags-y += -D__CHECK_ENDIAN__
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19
drivers/net/wireless/rtlwifi/rtl8192ee/Makefile
Normal file
19
drivers/net/wireless/rtlwifi/rtl8192ee/Makefile
Normal file
@ -0,0 +1,19 @@
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obj-m := rtl8192ee.o
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rtl8192ee-objs := \
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dm.o \
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fw.o \
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hw.o \
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led.o \
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phy.o \
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pwrseq.o \
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rf.o \
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sw.o \
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table.o \
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trx.o \
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obj-$(CONFIG_RTL8821AE) += rtl8192ee.o
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ccflags-y += -D__CHECK_ENDIAN__
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101
drivers/net/wireless/rtlwifi/rtl8192ee/def.h
Normal file
101
drivers/net/wireless/rtlwifi/rtl8192ee/def.h
Normal file
@ -0,0 +1,101 @@
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/******************************************************************************
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*
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* Copyright(c) 2009-2014 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __RTL92E_DEF_H__
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#define __RTL92E_DEF_H__
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#define RX_DESC_NUM_92E 512
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#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
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#define HAL_PRIME_CHNL_OFFSET_LOWER 1
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#define HAL_PRIME_CHNL_OFFSET_UPPER 2
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#define RX_MPDU_QUEUE 0
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#define IS_HT_RATE(_rate) \
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(_rate >= DESC92C_RATEMCS0)
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#define IS_CCK_RATE(_rate) \
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(_rate >= DESC92C_RATE1M && _rate <= DESC92C_RATE11M)
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#define IS_OFDM_RATE(_rate) \
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(_rate >= DESC92C_RATE6M && _rate <= DESC92C_RATE54M)
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enum version_8192e {
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VERSION_TEST_CHIP_2T2R_8192E = 0x0024,
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VERSION_NORMAL_CHIP_2T2R_8192E = 0x102C,
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VERSION_UNKNOWN = 0xFF,
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};
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enum rx_packet_type {
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NORMAL_RX,
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TX_REPORT1,
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TX_REPORT2,
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HIS_REPORT,
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C2H_PACKET,
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};
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enum rtl_desc_qsel {
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QSLT_BK = 0x2,
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QSLT_BE = 0x0,
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QSLT_VI = 0x5,
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QSLT_VO = 0x7,
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QSLT_BEACON = 0x10,
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QSLT_HIGH = 0x11,
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QSLT_MGNT = 0x12,
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QSLT_CMD = 0x13,
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};
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enum rtl_desc92c_rate {
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DESC92C_RATE1M = 0x00,
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DESC92C_RATE2M = 0x01,
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DESC92C_RATE5_5M = 0x02,
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DESC92C_RATE11M = 0x03,
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DESC92C_RATE6M = 0x04,
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DESC92C_RATE9M = 0x05,
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DESC92C_RATE12M = 0x06,
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DESC92C_RATE18M = 0x07,
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DESC92C_RATE24M = 0x08,
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DESC92C_RATE36M = 0x09,
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DESC92C_RATE48M = 0x0a,
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DESC92C_RATE54M = 0x0b,
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DESC92C_RATEMCS0 = 0x0c,
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DESC92C_RATEMCS1 = 0x0d,
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DESC92C_RATEMCS2 = 0x0e,
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DESC92C_RATEMCS3 = 0x0f,
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DESC92C_RATEMCS4 = 0x10,
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DESC92C_RATEMCS5 = 0x11,
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DESC92C_RATEMCS6 = 0x12,
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DESC92C_RATEMCS7 = 0x13,
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DESC92C_RATEMCS8 = 0x14,
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DESC92C_RATEMCS9 = 0x15,
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DESC92C_RATEMCS10 = 0x16,
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DESC92C_RATEMCS11 = 0x17,
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DESC92C_RATEMCS12 = 0x18,
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DESC92C_RATEMCS13 = 0x19,
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DESC92C_RATEMCS14 = 0x1a,
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DESC92C_RATEMCS15 = 0x1b,
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};
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#endif
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1263
drivers/net/wireless/rtlwifi/rtl8192ee/dm.c
Normal file
1263
drivers/net/wireless/rtlwifi/rtl8192ee/dm.c
Normal file
File diff suppressed because it is too large
Load Diff
267
drivers/net/wireless/rtlwifi/rtl8192ee/dm.h
Normal file
267
drivers/net/wireless/rtlwifi/rtl8192ee/dm.h
Normal file
@ -0,0 +1,267 @@
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/******************************************************************************
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*
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* Copyright(c) 2009-2014 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __RTL92E_DM_H__
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#define __RTL92E_DM_H__
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#define OFDMCCA_TH 500
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#define BW_IND_BIAS 500
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#define MF_USC 2
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#define MF_LSC 1
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#define MF_USC_LSC 0
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#define MONITOR_TIME 30
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#define MAIN_ANT 0
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#define AUX_ANT 1
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#define MAIN_ANT_CG_TRX 1
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#define AUX_ANT_CG_TRX 0
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#define MAIN_ANT_CGCS_RX 0
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#define AUX_ANT_CGCS_RX 1
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/*RF REG LIST*/
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#define DM_REG_RF_MODE_11N 0x00
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#define DM_REG_RF_0B_11N 0x0B
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#define DM_REG_CHNBW_11N 0x18
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#define DM_REG_T_METER_11N 0x24
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#define DM_REG_RF_25_11N 0x25
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#define DM_REG_RF_26_11N 0x26
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#define DM_REG_RF_27_11N 0x27
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#define DM_REG_RF_2B_11N 0x2B
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#define DM_REG_RF_2C_11N 0x2C
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#define DM_REG_RXRF_A3_11N 0x3C
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#define DM_REG_T_METER_92D_11N 0x42
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#define DM_REG_T_METER_92E_11N 0x42
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/*BB REG LIST*/
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/*PAGE 8 */
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#define DM_REG_BB_CTRL_11N 0x800
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#define DM_REG_RF_PIN_11N 0x804
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#define DM_REG_PSD_CTRL_11N 0x808
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#define DM_REG_TX_ANT_CTRL_11N 0x80C
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#define DM_REG_BB_PWR_SAV5_11N 0x818
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#define DM_REG_CCK_RPT_FORMAT_11N 0x824
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#define DM_REG_RX_DEFUALT_A_11N 0x858
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#define DM_REG_RX_DEFUALT_B_11N 0x85A
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#define DM_REG_BB_PWR_SAV3_11N 0x85C
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#define DM_REG_ANTSEL_CTRL_11N 0x860
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#define DM_REG_RX_ANT_CTRL_11N 0x864
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#define DM_REG_PIN_CTRL_11N 0x870
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#define DM_REG_BB_PWR_SAV1_11N 0x874
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#define DM_REG_ANTSEL_PATH_11N 0x878
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#define DM_REG_BB_3WIRE_11N 0x88C
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#define DM_REG_SC_CNT_11N 0x8C4
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#define DM_REG_PSD_DATA_11N 0x8B4
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/*PAGE 9*/
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#define DM_REG_ANT_MAPPING1_11N 0x914
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#define DM_REG_ANT_MAPPING2_11N 0x918
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/*PAGE A*/
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#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00
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#define DM_REG_CCK_CCA_11N 0xA0A
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#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
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#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10
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#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14
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#define DM_REG_CCK_FILTER_PARA1_11N 0xA22
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#define DM_REG_CCK_FILTER_PARA2_11N 0xA23
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#define DM_REG_CCK_FILTER_PARA3_11N 0xA24
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#define DM_REG_CCK_FILTER_PARA4_11N 0xA25
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#define DM_REG_CCK_FILTER_PARA5_11N 0xA26
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#define DM_REG_CCK_FILTER_PARA6_11N 0xA27
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#define DM_REG_CCK_FILTER_PARA7_11N 0xA28
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#define DM_REG_CCK_FILTER_PARA8_11N 0xA29
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#define DM_REG_CCK_FA_RST_11N 0xA2C
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#define DM_REG_CCK_FA_MSB_11N 0xA58
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#define DM_REG_CCK_FA_LSB_11N 0xA5C
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#define DM_REG_CCK_CCA_CNT_11N 0xA60
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#define DM_REG_BB_PWR_SAV4_11N 0xA74
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/*PAGE B */
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#define DM_REG_LNA_SWITCH_11N 0xB2C
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#define DM_REG_PATH_SWITCH_11N 0xB30
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#define DM_REG_RSSI_CTRL_11N 0xB38
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#define DM_REG_CONFIG_ANTA_11N 0xB68
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#define DM_REG_RSSI_BT_11N 0xB9C
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/*PAGE C */
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#define DM_REG_OFDM_FA_HOLDC_11N 0xC00
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#define DM_REG_RX_PATH_11N 0xC04
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#define DM_REG_TRMUX_11N 0xC08
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#define DM_REG_OFDM_FA_RSTC_11N 0xC0C
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#define DM_REG_RXIQI_MATRIX_11N 0xC14
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#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
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#define DM_REG_IGI_A_11N 0xC50
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#define DM_REG_ANTDIV_PARA2_11N 0xC54
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#define DM_REG_IGI_B_11N 0xC58
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#define DM_REG_ANTDIV_PARA3_11N 0xC5C
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#define DM_REG_L1SBD_PD_CH_11N 0XC6C
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#define DM_REG_BB_PWR_SAV2_11N 0xC70
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#define DM_REG_RX_OFF_11N 0xC7C
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#define DM_REG_TXIQK_MATRIXA_11N 0xC80
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#define DM_REG_TXIQK_MATRIXB_11N 0xC88
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#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
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#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
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#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
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#define DM_REG_ANTDIV_PARA1_11N 0xCA4
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#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0
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/*PAGE D */
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#define DM_REG_OFDM_FA_RSTD_11N 0xD00
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#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0
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#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4
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#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8
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/*PAGE E */
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#define DM_REG_TXAGC_A_6_18_11N 0xE00
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#define DM_REG_TXAGC_A_24_54_11N 0xE04
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#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08
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#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10
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#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14
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#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18
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#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C
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#define DM_REG_FPGA0_IQK_11N 0xE28
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#define DM_REG_TXIQK_TONE_A_11N 0xE30
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#define DM_REG_RXIQK_TONE_A_11N 0xE34
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#define DM_REG_TXIQK_PI_A_11N 0xE38
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#define DM_REG_RXIQK_PI_A_11N 0xE3C
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#define DM_REG_TXIQK_11N 0xE40
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#define DM_REG_RXIQK_11N 0xE44
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#define DM_REG_IQK_AGC_PTS_11N 0xE48
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#define DM_REG_IQK_AGC_RSP_11N 0xE4C
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#define DM_REG_BLUETOOTH_11N 0xE6C
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#define DM_REG_RX_WAIT_CCA_11N 0xE70
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#define DM_REG_TX_CCK_RFON_11N 0xE74
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#define DM_REG_TX_CCK_BBON_11N 0xE78
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#define DM_REG_OFDM_RFON_11N 0xE7C
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#define DM_REG_OFDM_BBON_11N 0xE80
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#define DM_REG_TX2RX_11N 0xE84
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#define DM_REG_TX2TX_11N 0xE88
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#define DM_REG_RX_CCK_11N 0xE8C
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#define DM_REG_RX_OFDM_11N 0xED0
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#define DM_REG_RX_WAIT_RIFS_11N 0xED4
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#define DM_REG_RX2RX_11N 0xED8
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#define DM_REG_STANDBY_11N 0xEDC
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#define DM_REG_SLEEP_11N 0xEE0
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#define DM_REG_PMPD_ANAEN_11N 0xEEC
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/*MAC REG LIST*/
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#define DM_REG_BB_RST_11N 0x02
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#define DM_REG_ANTSEL_PIN_11N 0x4C
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#define DM_REG_EARLY_MODE_11N 0x4D0
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#define DM_REG_RSSI_MONITOR_11N 0x4FE
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#define DM_REG_EDCA_VO_11N 0x500
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#define DM_REG_EDCA_VI_11N 0x504
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#define DM_REG_EDCA_BE_11N 0x508
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#define DM_REG_EDCA_BK_11N 0x50C
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#define DM_REG_TXPAUSE_11N 0x522
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#define DM_REG_RESP_TX_11N 0x6D8
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#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0
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#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4
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/*DIG Related*/
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#define DM_BIT_IGI_11N 0x0000007F
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#define HAL_DM_DIG_DISABLE BIT(0)
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#define HAL_DM_HIPWR_DISABLE BIT(1)
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#define OFDM_TABLE_LENGTH 43
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#define CCK_TABLE_LENGTH 33
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#define OFDM_TABLE_SIZE 43
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#define CCK_TABLE_SIZE 33
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#define BW_AUTO_SWITCH_HIGH_LOW 25
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#define BW_AUTO_SWITCH_LOW_HIGH 30
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#define DM_DIG_THRESH_HIGH 40
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#define DM_DIG_THRESH_LOW 35
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#define DM_FALSEALARM_THRESH_LOW 400
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#define DM_FALSEALARM_THRESH_HIGH 1000
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#define DM_DIG_MAX 0x3e
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#define DM_DIG_MIN 0x1e
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#define DM_DIG_MAX_AP 0x32
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#define DM_DIG_MIN_AP 0x20
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#define DM_DIG_FA_UPPER 0x3e
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#define DM_DIG_FA_LOWER 0x1e
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#define DM_DIG_FA_TH0 0x200
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#define DM_DIG_FA_TH1 0x300
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#define DM_DIG_FA_TH2 0x400
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#define DM_DIG_BACKOFF_MAX 12
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#define DM_DIG_BACKOFF_MIN -4
|
||||
#define DM_DIG_BACKOFF_DEFAULT 10
|
||||
|
||||
#define RXPATHSELECTION_SS_TH_LOW 30
|
||||
#define RXPATHSELECTION_DIFF_TH 18
|
||||
|
||||
#define DM_RATR_STA_INIT 0
|
||||
#define DM_RATR_STA_HIGH 1
|
||||
#define DM_RATR_STA_MIDDLE 2
|
||||
#define DM_RATR_STA_LOW 3
|
||||
|
||||
#define CTS2SELF_THVAL 30
|
||||
#define REGC38_TH 20
|
||||
|
||||
#define WAIOTTHVAL 25
|
||||
|
||||
#define TXHIGHPWRLEVEL_NORMAL 0
|
||||
#define TXHIGHPWRLEVEL_LEVEL1 1
|
||||
#define TXHIGHPWRLEVEL_LEVEL2 2
|
||||
#define TXHIGHPWRLEVEL_BT1 3
|
||||
#define TXHIGHPWRLEVEL_BT2 4
|
||||
|
||||
#define DM_TYPE_BYFW 0
|
||||
#define DM_TYPE_BYDRIVER 1
|
||||
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
|
||||
#define TXPWRTRACK_MAX_IDX 6
|
||||
|
||||
/* Dynamic ATC switch */
|
||||
#define ATC_STATUS_OFF 0x0 /* enable */
|
||||
#define ATC_STATUS_ON 0x1 /* disable */
|
||||
#define CFO_THRESHOLD_XTAL 10 /* kHz */
|
||||
#define CFO_THRESHOLD_ATC 80 /* kHz */
|
||||
|
||||
/* RSSI Dump Message */
|
||||
#define RA_RSSIDUMP 0xcb0
|
||||
#define RB_RSSIDUMP 0xcb1
|
||||
#define RS1_RXEVMDUMP 0xcb2
|
||||
#define RS2_RXEVMDUMP 0xcb3
|
||||
#define RA_RXSNRDUMP 0xcb4
|
||||
#define RB_RXSNRDUMP 0xcb5
|
||||
#define RA_CFOSHORTDUMP 0xcb6
|
||||
#define RB_CFOSHORTDUMP 0xcb8
|
||||
#define RA_CFOLONGDUMP 0xcba
|
||||
#define RB_CFOLONGDUMP 0xcbc
|
||||
|
||||
void rtl92ee_dm_init(struct ieee80211_hw *hw);
|
||||
void rtl92ee_dm_watchdog(struct ieee80211_hw *hw);
|
||||
void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw,
|
||||
u8 cur_thres);
|
||||
void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
|
||||
void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw);
|
||||
void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
|
||||
void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw,
|
||||
u8 rate, bool collision_state);
|
||||
#endif
|
||||
936
drivers/net/wireless/rtlwifi/rtl8192ee/fw.c
Normal file
936
drivers/net/wireless/rtlwifi/rtl8192ee/fw.c
Normal file
@ -0,0 +1,936 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "../wifi.h"
|
||||
#include "../pci.h"
|
||||
#include "../base.h"
|
||||
#include "reg.h"
|
||||
#include "def.h"
|
||||
#include "fw.h"
|
||||
#include "dm.h"
|
||||
|
||||
static void _rtl92ee_enable_fw_download(struct ieee80211_hw *hw, bool enable)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
u8 tmp;
|
||||
|
||||
if (enable) {
|
||||
rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x05);
|
||||
|
||||
tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
|
||||
rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
|
||||
} else {
|
||||
tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
|
||||
rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
|
||||
}
|
||||
}
|
||||
|
||||
static void _rtl92ee_fw_block_write(struct ieee80211_hw *hw,
|
||||
const u8 *buffer, u32 size)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
u32 blocksize = sizeof(u32);
|
||||
u8 *bufferptr = (u8 *)buffer;
|
||||
u32 *pu4byteptr = (u32 *)buffer;
|
||||
u32 i, offset, blockcount, remainsize;
|
||||
|
||||
blockcount = size / blocksize;
|
||||
remainsize = size % blocksize;
|
||||
|
||||
for (i = 0; i < blockcount; i++) {
|
||||
offset = i * blocksize;
|
||||
rtl_write_dword(rtlpriv, (FW_8192C_START_ADDRESS + offset),
|
||||
*(pu4byteptr + i));
|
||||
}
|
||||
|
||||
if (remainsize) {
|
||||
offset = blockcount * blocksize;
|
||||
bufferptr += offset;
|
||||
for (i = 0; i < remainsize; i++) {
|
||||
rtl_write_byte(rtlpriv,
|
||||
(FW_8192C_START_ADDRESS + offset + i),
|
||||
*(bufferptr + i));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void _rtl92ee_fw_page_write(struct ieee80211_hw *hw, u32 page,
|
||||
const u8 *buffer, u32 size)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
u8 value8;
|
||||
u8 u8page = (u8)(page & 0x07);
|
||||
|
||||
value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
|
||||
rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
|
||||
|
||||
_rtl92ee_fw_block_write(hw, buffer, size);
|
||||
}
|
||||
|
||||
static void _rtl92ee_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
|
||||
{
|
||||
u32 fwlen = *pfwlen;
|
||||
u8 remain = (u8)(fwlen % 4);
|
||||
|
||||
remain = (remain == 0) ? 0 : (4 - remain);
|
||||
|
||||
while (remain > 0) {
|
||||
pfwbuf[fwlen] = 0;
|
||||
fwlen++;
|
||||
remain--;
|
||||
}
|
||||
|
||||
*pfwlen = fwlen;
|
||||
}
|
||||
|
||||
static void _rtl92ee_write_fw(struct ieee80211_hw *hw,
|
||||
enum version_8192e version,
|
||||
u8 *buffer, u32 size)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
u8 *bufferptr = (u8 *)buffer;
|
||||
u32 pagenums, remainsize;
|
||||
u32 page, offset;
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "FW size is %d bytes,\n", size);
|
||||
|
||||
_rtl92ee_fill_dummy(bufferptr, &size);
|
||||
|
||||
pagenums = size / FW_8192C_PAGE_SIZE;
|
||||
remainsize = size % FW_8192C_PAGE_SIZE;
|
||||
|
||||
if (pagenums > 8) {
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
|
||||
"Page numbers should not greater then 8\n");
|
||||
}
|
||||
|
||||
for (page = 0; page < pagenums; page++) {
|
||||
offset = page * FW_8192C_PAGE_SIZE;
|
||||
_rtl92ee_fw_page_write(hw, page, (bufferptr + offset),
|
||||
FW_8192C_PAGE_SIZE);
|
||||
udelay(2);
|
||||
}
|
||||
|
||||
if (remainsize) {
|
||||
offset = pagenums * FW_8192C_PAGE_SIZE;
|
||||
page = pagenums;
|
||||
_rtl92ee_fw_page_write(hw, page, (bufferptr + offset),
|
||||
remainsize);
|
||||
}
|
||||
}
|
||||
|
||||
static int _rtl92ee_fw_free_to_go(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
int err = -EIO;
|
||||
u32 counter = 0;
|
||||
u32 value32;
|
||||
|
||||
do {
|
||||
value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
|
||||
} while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&
|
||||
(!(value32 & FWDL_CHKSUM_RPT)));
|
||||
|
||||
if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
|
||||
"chksum report faill ! REG_MCUFWDL:0x%08x .\n",
|
||||
value32);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
|
||||
"Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32);
|
||||
|
||||
value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
|
||||
value32 |= MCUFWDL_RDY;
|
||||
value32 &= ~WINTINI_RDY;
|
||||
rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
|
||||
|
||||
rtl92ee_firmware_selfreset(hw);
|
||||
counter = 0;
|
||||
|
||||
do {
|
||||
value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
|
||||
if (value32 & WINTINI_RDY) {
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD ,
|
||||
"Polling FW ready success!! REG_MCUFWDL:0x%08x. count = %d\n",
|
||||
value32, counter);
|
||||
err = 0;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
udelay(FW_8192C_POLLING_DELAY*10);
|
||||
|
||||
} while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT);
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
|
||||
"Polling FW ready fail!! REG_MCUFWDL:0x%08x. count = %d\n",
|
||||
value32, counter);
|
||||
|
||||
exit:
|
||||
return err;
|
||||
}
|
||||
|
||||
int rtl92ee_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
|
||||
struct rtl92c_firmware_header *pfwheader;
|
||||
u8 *pfwdata;
|
||||
u32 fwsize;
|
||||
int err;
|
||||
enum version_8192e version = rtlhal->version;
|
||||
|
||||
if (!rtlhal->pfirmware)
|
||||
return 1;
|
||||
|
||||
pfwheader = (struct rtl92c_firmware_header *)rtlhal->pfirmware;
|
||||
rtlhal->fw_version = pfwheader->version;
|
||||
rtlhal->fw_subversion = pfwheader->subversion;
|
||||
pfwdata = (u8 *)rtlhal->pfirmware;
|
||||
fwsize = rtlhal->fwsize;
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
|
||||
"normal Firmware SIZE %d\n" , fwsize);
|
||||
|
||||
if (IS_FW_HEADER_EXIST(pfwheader)) {
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
|
||||
"Firmware Version(%d), Signature(%#x),Size(%d)\n",
|
||||
pfwheader->version, pfwheader->signature,
|
||||
(int)sizeof(struct rtl92c_firmware_header));
|
||||
|
||||
pfwdata = pfwdata + sizeof(struct rtl92c_firmware_header);
|
||||
fwsize = fwsize - sizeof(struct rtl92c_firmware_header);
|
||||
} else {
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
|
||||
"Firmware no Header, Signature(%#x)\n",
|
||||
pfwheader->signature);
|
||||
}
|
||||
|
||||
if (rtlhal->mac_func_enable) {
|
||||
if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) {
|
||||
rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
|
||||
rtl92ee_firmware_selfreset(hw);
|
||||
}
|
||||
}
|
||||
_rtl92ee_enable_fw_download(hw, true);
|
||||
_rtl92ee_write_fw(hw, version, pfwdata, fwsize);
|
||||
_rtl92ee_enable_fw_download(hw, false);
|
||||
|
||||
err = _rtl92ee_fw_free_to_go(hw);
|
||||
if (err) {
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
|
||||
"Firmware is not ready to run!\n");
|
||||
} else {
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD ,
|
||||
"Firmware is ready to run!\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool _rtl92ee_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
u8 val_hmetfr;
|
||||
bool result = false;
|
||||
|
||||
val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
|
||||
if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
|
||||
result = true;
|
||||
return result;
|
||||
}
|
||||
|
||||
static void _rtl92ee_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
|
||||
u32 cmd_len, u8 *cmdbuffer)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
|
||||
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
|
||||
u8 boxnum;
|
||||
u16 box_reg = 0, box_extreg = 0;
|
||||
u8 u1b_tmp;
|
||||
bool isfw_read = false;
|
||||
u8 buf_index = 0;
|
||||
bool bwrite_sucess = false;
|
||||
u8 wait_h2c_limmit = 100;
|
||||
u8 boxcontent[4], boxextcontent[4];
|
||||
u32 h2c_waitcounter = 0;
|
||||
unsigned long flag;
|
||||
u8 idx;
|
||||
|
||||
if (ppsc->dot11_psmode != EACTIVE ||
|
||||
ppsc->inactive_pwrstate == ERFOFF) {
|
||||
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
|
||||
"FillH2CCommand8192E(): Return because RF is off!!!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD , "come in\n");
|
||||
|
||||
/* 1. Prevent race condition in setting H2C cmd.
|
||||
* (copy from MgntActSet_RF_State().)
|
||||
*/
|
||||
while (true) {
|
||||
spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
|
||||
if (rtlhal->h2c_setinprogress) {
|
||||
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
|
||||
"H2C set in progress! Wait to set..element_id(%d).\n",
|
||||
element_id);
|
||||
|
||||
while (rtlhal->h2c_setinprogress) {
|
||||
spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
|
||||
flag);
|
||||
h2c_waitcounter++;
|
||||
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
|
||||
"Wait 100 us (%d times)...\n",
|
||||
h2c_waitcounter);
|
||||
udelay(100);
|
||||
|
||||
if (h2c_waitcounter > 1000)
|
||||
return;
|
||||
spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
|
||||
flag);
|
||||
}
|
||||
spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
|
||||
} else {
|
||||
rtlhal->h2c_setinprogress = true;
|
||||
spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
while (!bwrite_sucess) {
|
||||
/* 2. Find the last BOX number which has been writen. */
|
||||
boxnum = rtlhal->last_hmeboxnum;
|
||||
switch (boxnum) {
|
||||
case 0:
|
||||
box_reg = REG_HMEBOX_0;
|
||||
box_extreg = REG_HMEBOX_EXT_0;
|
||||
break;
|
||||
case 1:
|
||||
box_reg = REG_HMEBOX_1;
|
||||
box_extreg = REG_HMEBOX_EXT_1;
|
||||
break;
|
||||
case 2:
|
||||
box_reg = REG_HMEBOX_2;
|
||||
box_extreg = REG_HMEBOX_EXT_2;
|
||||
break;
|
||||
case 3:
|
||||
box_reg = REG_HMEBOX_3;
|
||||
box_extreg = REG_HMEBOX_EXT_3;
|
||||
break;
|
||||
default:
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
|
||||
"switch case not process\n");
|
||||
break;
|
||||
}
|
||||
|
||||
/* 3. Check if the box content is empty. */
|
||||
isfw_read = false;
|
||||
u1b_tmp = rtl_read_byte(rtlpriv, REG_CR);
|
||||
|
||||
if (u1b_tmp != 0xea) {
|
||||
isfw_read = true;
|
||||
} else {
|
||||
if (rtl_read_byte(rtlpriv, REG_TXDMA_STATUS) == 0xea ||
|
||||
rtl_read_byte(rtlpriv, REG_TXPKT_EMPTY) == 0xea)
|
||||
rtl_write_byte(rtlpriv, REG_SYS_CFG1 + 3, 0xff);
|
||||
}
|
||||
|
||||
if (isfw_read) {
|
||||
wait_h2c_limmit = 100;
|
||||
isfw_read = _rtl92ee_check_fw_read_last_h2c(hw, boxnum);
|
||||
while (!isfw_read) {
|
||||
wait_h2c_limmit--;
|
||||
if (wait_h2c_limmit == 0) {
|
||||
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
|
||||
"Waiting too long for FW read clear HMEBox(%d)!!!\n",
|
||||
boxnum);
|
||||
break;
|
||||
}
|
||||
udelay(10);
|
||||
isfw_read =
|
||||
_rtl92ee_check_fw_read_last_h2c(hw, boxnum);
|
||||
u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
|
||||
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
|
||||
"Waiting for FW read clear HMEBox(%d)!!! 0x130 = %2x\n",
|
||||
boxnum, u1b_tmp);
|
||||
}
|
||||
}
|
||||
|
||||
/* If Fw has not read the last
|
||||
* H2C cmd, break and give up this H2C.
|
||||
*/
|
||||
if (!isfw_read) {
|
||||
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
|
||||
"Write H2C reg BOX[%d] fail,Fw don't read.\n",
|
||||
boxnum);
|
||||
break;
|
||||
}
|
||||
/* 4. Fill the H2C cmd into box */
|
||||
memset(boxcontent, 0, sizeof(boxcontent));
|
||||
memset(boxextcontent, 0, sizeof(boxextcontent));
|
||||
boxcontent[0] = element_id;
|
||||
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
|
||||
"Write element_id box_reg(%4x) = %2x\n",
|
||||
box_reg, element_id);
|
||||
|
||||
switch (cmd_len) {
|
||||
case 1:
|
||||
case 2:
|
||||
case 3:
|
||||
/*boxcontent[0] &= ~(BIT(7));*/
|
||||
memcpy((u8 *)(boxcontent) + 1,
|
||||
cmdbuffer + buf_index, cmd_len);
|
||||
|
||||
for (idx = 0; idx < 4; idx++) {
|
||||
rtl_write_byte(rtlpriv, box_reg + idx,
|
||||
boxcontent[idx]);
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
case 5:
|
||||
case 6:
|
||||
case 7:
|
||||
/*boxcontent[0] |= (BIT(7));*/
|
||||
memcpy((u8 *)(boxextcontent),
|
||||
cmdbuffer + buf_index+3, cmd_len-3);
|
||||
memcpy((u8 *)(boxcontent) + 1,
|
||||
cmdbuffer + buf_index, 3);
|
||||
|
||||
for (idx = 0; idx < 4; idx++) {
|
||||
rtl_write_byte(rtlpriv, box_extreg + idx,
|
||||
boxextcontent[idx]);
|
||||
}
|
||||
|
||||
for (idx = 0; idx < 4; idx++) {
|
||||
rtl_write_byte(rtlpriv, box_reg + idx,
|
||||
boxcontent[idx]);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
|
||||
"switch case not process\n");
|
||||
break;
|
||||
}
|
||||
|
||||
bwrite_sucess = true;
|
||||
|
||||
rtlhal->last_hmeboxnum = boxnum + 1;
|
||||
if (rtlhal->last_hmeboxnum == 4)
|
||||
rtlhal->last_hmeboxnum = 0;
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
|
||||
"pHalData->last_hmeboxnum = %d\n",
|
||||
rtlhal->last_hmeboxnum);
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
|
||||
rtlhal->h2c_setinprogress = false;
|
||||
spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD , "go out\n");
|
||||
}
|
||||
|
||||
void rtl92ee_fill_h2c_cmd(struct ieee80211_hw *hw,
|
||||
u8 element_id, u32 cmd_len, u8 *cmdbuffer)
|
||||
{
|
||||
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
|
||||
u32 tmp_cmdbuf[2];
|
||||
|
||||
if (!rtlhal->fw_ready) {
|
||||
RT_ASSERT(false,
|
||||
"return H2C cmd because of Fw download fail!!!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
memset(tmp_cmdbuf, 0, 8);
|
||||
memcpy(tmp_cmdbuf, cmdbuffer, cmd_len);
|
||||
_rtl92ee_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
|
||||
}
|
||||
|
||||
void rtl92ee_firmware_selfreset(struct ieee80211_hw *hw)
|
||||
{
|
||||
u8 u1b_tmp;
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
|
||||
u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
|
||||
rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
|
||||
|
||||
u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
|
||||
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
|
||||
|
||||
udelay(50);
|
||||
|
||||
u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
|
||||
rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0)));
|
||||
|
||||
u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
|
||||
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp | BIT(2)));
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD ,
|
||||
" _8051Reset92E(): 8051 reset success .\n");
|
||||
}
|
||||
|
||||
void rtl92ee_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
u8 u1_h2c_set_pwrmode[H2C_92E_PWEMODE_LENGTH] = { 0 };
|
||||
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
|
||||
u8 rlbm , power_state = 0;
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD , "FW LPS mode = %d\n", mode);
|
||||
|
||||
SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
|
||||
rlbm = 0;/*YJ,temp,120316. FW now not support RLBM=2.*/
|
||||
SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, rlbm);
|
||||
SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
|
||||
(rtlpriv->mac80211.p2p) ?
|
||||
ppsc->smart_ps : 1);
|
||||
SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode,
|
||||
ppsc->reg_max_lps_awakeintvl);
|
||||
SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
|
||||
if (mode == FW_PS_ACTIVE_MODE)
|
||||
power_state |= FW_PWR_STATE_ACTIVE;
|
||||
else
|
||||
power_state |= FW_PWR_STATE_RF_OFF;
|
||||
SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1_h2c_set_pwrmode, power_state);
|
||||
|
||||
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
|
||||
"rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode\n",
|
||||
u1_h2c_set_pwrmode, H2C_92E_PWEMODE_LENGTH);
|
||||
rtl92ee_fill_h2c_cmd(hw, H2C_92E_SETPWRMODE, H2C_92E_PWEMODE_LENGTH,
|
||||
u1_h2c_set_pwrmode);
|
||||
}
|
||||
|
||||
void rtl92ee_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus)
|
||||
{
|
||||
u8 parm[3] = { 0 , 0 , 0 };
|
||||
/* parm[0]: bit0=0-->Disconnect, bit0=1-->Connect
|
||||
* bit1=0-->update Media Status to MACID
|
||||
* bit1=1-->update Media Status from MACID to MACID_End
|
||||
* parm[1]: MACID, if this is INFRA_STA, MacID = 0
|
||||
* parm[2]: MACID_End
|
||||
*/
|
||||
|
||||
SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, mstatus);
|
||||
SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0);
|
||||
|
||||
rtl92ee_fill_h2c_cmd(hw, H2C_92E_MSRRPT, 3, parm);
|
||||
}
|
||||
|
||||
static bool _rtl92ee_cmd_send_packet(struct ieee80211_hw *hw,
|
||||
struct sk_buff *skb)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
|
||||
struct rtl8192_tx_ring *ring;
|
||||
struct rtl_tx_desc *pdesc;
|
||||
unsigned long flags;
|
||||
struct sk_buff *pskb = NULL;
|
||||
|
||||
ring = &rtlpci->tx_ring[BEACON_QUEUE];
|
||||
|
||||
pskb = __skb_dequeue(&ring->queue);
|
||||
if (pskb)
|
||||
kfree_skb(pskb);
|
||||
|
||||
spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
|
||||
/*this is wrong, fill_tx_cmddesc needs update*/
|
||||
pdesc = &ring->desc[0];
|
||||
|
||||
rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb);
|
||||
|
||||
__skb_queue_tail(&ring->queue, skb);
|
||||
|
||||
spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
|
||||
|
||||
rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
#define BEACON_PG 0 /* ->1 */
|
||||
#define PSPOLL_PG 2
|
||||
#define NULL_PG 3
|
||||
#define PROBERSP_PG 4 /* ->5 */
|
||||
|
||||
#define TOTAL_RESERVED_PKT_LEN 768
|
||||
|
||||
static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
|
||||
/* page 0 beacon */
|
||||
0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
|
||||
0xEC, 0x1A, 0x59, 0x0B, 0xAD, 0xD4, 0x20, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x64, 0x00, 0x10, 0x04, 0x00, 0x05, 0x54, 0x65,
|
||||
0x73, 0x74, 0x32, 0x01, 0x08, 0x82, 0x84, 0x0B,
|
||||
0x16, 0x24, 0x30, 0x48, 0x6C, 0x03, 0x01, 0x06,
|
||||
0x06, 0x02, 0x00, 0x00, 0x2A, 0x01, 0x02, 0x32,
|
||||
0x04, 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C,
|
||||
0x09, 0x03, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x3D, 0x00, 0xDD, 0x07, 0x00, 0xE0, 0x4C,
|
||||
0x02, 0x02, 0x00, 0x00, 0xDD, 0x18, 0x00, 0x50,
|
||||
0xF2, 0x01, 0x01, 0x00, 0x00, 0x50, 0xF2, 0x04,
|
||||
0x01, 0x00, 0x00, 0x50, 0xF2, 0x04, 0x01, 0x00,
|
||||
|
||||
/* page 1 beacon */
|
||||
0x00, 0x50, 0xF2, 0x02, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x10, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
|
||||
/* page 2 ps-poll */
|
||||
0xA4, 0x10, 0x01, 0xC0, 0xEC, 0x1A, 0x59, 0x0B,
|
||||
0xAD, 0xD4, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x18, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
|
||||
/* page 3 null */
|
||||
0x48, 0x01, 0x00, 0x00, 0xEC, 0x1A, 0x59, 0x0B,
|
||||
0xAD, 0xD4, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
|
||||
0xEC, 0x1A, 0x59, 0x0B, 0xAD, 0xD4, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x72, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
|
||||
/* page 4 probe_resp */
|
||||
0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
|
||||
0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
|
||||
0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
|
||||
0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
|
||||
0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
|
||||
0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
|
||||
0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
|
||||
0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
|
||||
0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
|
||||
0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
|
||||
0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
|
||||
/* page 5 probe_resp */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
};
|
||||
|
||||
void rtl92ee_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
|
||||
struct sk_buff *skb = NULL;
|
||||
|
||||
u32 totalpacketlen;
|
||||
bool rtstatus;
|
||||
u8 u1rsvdpageloc[5] = { 0 };
|
||||
bool b_dlok = false;
|
||||
|
||||
u8 *beacon;
|
||||
u8 *p_pspoll;
|
||||
u8 *nullfunc;
|
||||
u8 *p_probersp;
|
||||
/*---------------------------------------------------------
|
||||
* (1) beacon
|
||||
*---------------------------------------------------------
|
||||
*/
|
||||
beacon = &reserved_page_packet[BEACON_PG * 128];
|
||||
SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
|
||||
SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
|
||||
|
||||
/*-------------------------------------------------------
|
||||
* (2) ps-poll
|
||||
*--------------------------------------------------------
|
||||
*/
|
||||
p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
|
||||
SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
|
||||
SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
|
||||
SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
|
||||
|
||||
SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1rsvdpageloc, PSPOLL_PG);
|
||||
|
||||
/*--------------------------------------------------------
|
||||
* (3) null data
|
||||
*---------------------------------------------------------
|
||||
*/
|
||||
nullfunc = &reserved_page_packet[NULL_PG * 128];
|
||||
SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
|
||||
SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
|
||||
SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
|
||||
|
||||
SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1rsvdpageloc, NULL_PG);
|
||||
|
||||
/*---------------------------------------------------------
|
||||
* (4) probe response
|
||||
*----------------------------------------------------------
|
||||
*/
|
||||
p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
|
||||
SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
|
||||
SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
|
||||
SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
|
||||
|
||||
SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1rsvdpageloc, PROBERSP_PG);
|
||||
|
||||
totalpacketlen = TOTAL_RESERVED_PKT_LEN;
|
||||
|
||||
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD ,
|
||||
"rtl92ee_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
|
||||
&reserved_page_packet[0], totalpacketlen);
|
||||
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD ,
|
||||
"rtl92ee_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
|
||||
u1rsvdpageloc, 3);
|
||||
|
||||
skb = dev_alloc_skb(totalpacketlen);
|
||||
memcpy((u8 *)skb_put(skb, totalpacketlen),
|
||||
&reserved_page_packet, totalpacketlen);
|
||||
|
||||
rtstatus = _rtl92ee_cmd_send_packet(hw, skb);
|
||||
|
||||
if (rtstatus)
|
||||
b_dlok = true;
|
||||
|
||||
if (b_dlok) {
|
||||
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD ,
|
||||
"Set RSVD page location to Fw.\n");
|
||||
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD ,
|
||||
"H2C_RSVDPAGE:\n", u1rsvdpageloc, 3);
|
||||
rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSVDPAGE,
|
||||
sizeof(u1rsvdpageloc), u1rsvdpageloc);
|
||||
} else {
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
|
||||
"Set RSVD page location to Fw FAIL!!!!!!.\n");
|
||||
}
|
||||
}
|
||||
|
||||
/*Shoud check FW support p2p or not.*/
|
||||
static void rtl92ee_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw, u8 ctwindow)
|
||||
{
|
||||
u8 u1_ctwindow_period[1] = {ctwindow};
|
||||
|
||||
rtl92ee_fill_h2c_cmd(hw, H2C_92E_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
|
||||
}
|
||||
|
||||
void rtl92ee_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
|
||||
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
|
||||
struct rtl_p2p_ps_info *p2pinfo = &rtlps->p2p_ps_info;
|
||||
struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
|
||||
u8 i;
|
||||
u16 ctwindow;
|
||||
u32 start_time, tsf_low;
|
||||
|
||||
switch (p2p_ps_state) {
|
||||
case P2P_PS_DISABLE:
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "P2P_PS_DISABLE\n");
|
||||
memset(p2p_ps_offload, 0, sizeof(*p2p_ps_offload));
|
||||
break;
|
||||
case P2P_PS_ENABLE:
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "P2P_PS_ENABLE\n");
|
||||
/* update CTWindow value. */
|
||||
if (p2pinfo->ctwindow > 0) {
|
||||
p2p_ps_offload->ctwindow_en = 1;
|
||||
ctwindow = p2pinfo->ctwindow;
|
||||
rtl92ee_set_p2p_ctw_period_cmd(hw, ctwindow);
|
||||
}
|
||||
/* hw only support 2 set of NoA */
|
||||
for (i = 0 ; i < p2pinfo->noa_num ; i++) {
|
||||
/* To control the register setting for which NOA*/
|
||||
rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
|
||||
if (i == 0)
|
||||
p2p_ps_offload->noa0_en = 1;
|
||||
else
|
||||
p2p_ps_offload->noa1_en = 1;
|
||||
/* config P2P NoA Descriptor Register */
|
||||
rtl_write_dword(rtlpriv, 0x5E0,
|
||||
p2pinfo->noa_duration[i]);
|
||||
rtl_write_dword(rtlpriv, 0x5E4,
|
||||
p2pinfo->noa_interval[i]);
|
||||
|
||||
/*Get Current TSF value */
|
||||
tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
|
||||
|
||||
start_time = p2pinfo->noa_start_time[i];
|
||||
if (p2pinfo->noa_count_type[i] != 1) {
|
||||
while (start_time <= (tsf_low + (50 * 1024))) {
|
||||
start_time += p2pinfo->noa_interval[i];
|
||||
if (p2pinfo->noa_count_type[i] != 255)
|
||||
p2pinfo->noa_count_type[i]--;
|
||||
}
|
||||
}
|
||||
rtl_write_dword(rtlpriv, 0x5E8, start_time);
|
||||
rtl_write_dword(rtlpriv, 0x5EC,
|
||||
p2pinfo->noa_count_type[i]);
|
||||
}
|
||||
if ((p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0)) {
|
||||
/* rst p2p circuit */
|
||||
rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
|
||||
p2p_ps_offload->offload_en = 1;
|
||||
|
||||
if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
|
||||
p2p_ps_offload->role = 1;
|
||||
p2p_ps_offload->allstasleep = 0;
|
||||
} else {
|
||||
p2p_ps_offload->role = 0;
|
||||
}
|
||||
p2p_ps_offload->discovery = 0;
|
||||
}
|
||||
break;
|
||||
case P2P_PS_SCAN:
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "P2P_PS_SCAN\n");
|
||||
p2p_ps_offload->discovery = 1;
|
||||
break;
|
||||
case P2P_PS_SCAN_DONE:
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "P2P_PS_SCAN_DONE\n");
|
||||
p2p_ps_offload->discovery = 0;
|
||||
p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
rtl92ee_fill_h2c_cmd(hw, H2C_92E_P2P_PS_OFFLOAD, 1,
|
||||
(u8 *)p2p_ps_offload);
|
||||
}
|
||||
|
||||
static void _rtl92ee_c2h_ra_report_handler(struct ieee80211_hw *hw,
|
||||
u8 *cmd_buf, u8 cmd_len)
|
||||
{
|
||||
u8 rate = cmd_buf[0] & 0x3F;
|
||||
bool collision_state = cmd_buf[3] & BIT(0);
|
||||
|
||||
rtl92ee_dm_dynamic_arfb_select(hw, rate, collision_state);
|
||||
}
|
||||
|
||||
static void _rtl92ee_c2h_content_parsing(struct ieee80211_hw *hw, u8 c2h_cmd_id,
|
||||
u8 c2h_cmd_len, u8 *tmp_buf)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
|
||||
switch (c2h_cmd_id) {
|
||||
case C2H_8192E_DBG:
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
|
||||
"[C2H], C2H_8723BE_DBG!!\n");
|
||||
break;
|
||||
case C2H_8192E_TXBF:
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
|
||||
"[C2H], C2H_8192E_TXBF!!\n");
|
||||
break;
|
||||
case C2H_8192E_TX_REPORT:
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE ,
|
||||
"[C2H], C2H_8723BE_TX_REPORT!\n");
|
||||
break;
|
||||
case C2H_8192E_BT_INFO:
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
|
||||
"[C2H], C2H_8723BE_BT_INFO!!\n");
|
||||
rtlpriv->btcoexist.btc_ops->btc_btinfo_notify(rtlpriv, tmp_buf,
|
||||
c2h_cmd_len);
|
||||
break;
|
||||
case C2H_8192E_BT_MP:
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
|
||||
"[C2H], C2H_8723BE_BT_MP!!\n");
|
||||
break;
|
||||
case C2H_8192E_RA_RPT:
|
||||
_rtl92ee_c2h_ra_report_handler(hw, tmp_buf, c2h_cmd_len);
|
||||
break;
|
||||
default:
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
|
||||
"[C2H], Unkown packet!! CmdId(%#X)!\n", c2h_cmd_id);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rtl92ee_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 len)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
u8 c2h_cmd_id = 0, c2h_cmd_seq = 0, c2h_cmd_len = 0;
|
||||
u8 *tmp_buf = NULL;
|
||||
|
||||
c2h_cmd_id = buffer[0];
|
||||
c2h_cmd_seq = buffer[1];
|
||||
c2h_cmd_len = len - 2;
|
||||
tmp_buf = buffer + 2;
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
|
||||
"[C2H packet], c2hCmdId=0x%x, c2hCmdSeq=0x%x, c2hCmdLen=%d\n",
|
||||
c2h_cmd_id, c2h_cmd_seq, c2h_cmd_len);
|
||||
|
||||
RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_TRACE,
|
||||
"[C2H packet], Content Hex:\n", tmp_buf, c2h_cmd_len);
|
||||
|
||||
_rtl92ee_c2h_content_parsing(hw, c2h_cmd_id, c2h_cmd_len, tmp_buf);
|
||||
}
|
||||
208
drivers/net/wireless/rtlwifi/rtl8192ee/fw.h
Normal file
208
drivers/net/wireless/rtlwifi/rtl8192ee/fw.h
Normal file
@ -0,0 +1,208 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL92E__FW__H__
|
||||
#define __RTL92E__FW__H__
|
||||
|
||||
#define FW_8192C_SIZE 0x8000
|
||||
#define FW_8192C_START_ADDRESS 0x1000
|
||||
#define FW_8192C_END_ADDRESS 0x5FFF
|
||||
#define FW_8192C_PAGE_SIZE 4096
|
||||
#define FW_8192C_POLLING_DELAY 5
|
||||
#define FW_8192C_POLLING_TIMEOUT_COUNT 3000
|
||||
|
||||
#define IS_FW_HEADER_EXIST(_pfwhdr) \
|
||||
((_pfwhdr->signature&0xFFF0) == 0x92E0)
|
||||
#define USE_OLD_WOWLAN_DEBUG_FW 0
|
||||
|
||||
#define H2C_92E_RSVDPAGE_LOC_LEN 5
|
||||
#define H2C_92E_PWEMODE_LENGTH 5
|
||||
#define H2C_92E_JOINBSSRPT_LENGTH 1
|
||||
#define H2C_92E_AP_OFFLOAD_LENGTH 3
|
||||
#define H2C_92E_WOWLAN_LENGTH 3
|
||||
#define H2C_92E_KEEP_ALIVE_CTRL_LENGTH 3
|
||||
#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
|
||||
#define H2C_92E_REMOTE_WAKE_CTRL_LEN 1
|
||||
#else
|
||||
#define H2C_92E_REMOTE_WAKE_CTRL_LEN 3
|
||||
#endif
|
||||
#define H2C_92E_AOAC_GLOBAL_INFO_LEN 2
|
||||
#define H2C_92E_AOAC_RSVDPAGE_LOC_LEN 7
|
||||
|
||||
/* Fw PS state for RPWM.
|
||||
*BIT[2:0] = HW state
|
||||
*BIT[3] = Protocol PS state, 1: register active state, 0: register sleep state
|
||||
*BIT[4] = sub-state
|
||||
*/
|
||||
#define FW_PS_RF_ON BIT(2)
|
||||
#define FW_PS_REGISTER_ACTIVE BIT(3)
|
||||
|
||||
#define FW_PS_ACK BIT(6)
|
||||
#define FW_PS_TOGGLE BIT(7)
|
||||
|
||||
/* 92E RPWM value*/
|
||||
/* BIT[0] = 1: 32k, 0: 40M*/
|
||||
#define FW_PS_CLOCK_OFF BIT(0) /* 32k */
|
||||
#define FW_PS_CLOCK_ON 0 /* 40M */
|
||||
|
||||
#define FW_PS_STATE_MASK (0x0F)
|
||||
#define FW_PS_STATE_HW_MASK (0x07)
|
||||
#define FW_PS_STATE_INT_MASK (0x3F)
|
||||
|
||||
#define FW_PS_STATE(x) (FW_PS_STATE_MASK & (x))
|
||||
|
||||
#define FW_PS_STATE_ALL_ON_92E (FW_PS_CLOCK_ON)
|
||||
#define FW_PS_STATE_RF_ON_92E (FW_PS_CLOCK_ON)
|
||||
#define FW_PS_STATE_RF_OFF_92E (FW_PS_CLOCK_ON)
|
||||
#define FW_PS_STATE_RF_OFF_LOW_PWR (FW_PS_CLOCK_OFF)
|
||||
|
||||
/* For 92E H2C PwrMode Cmd ID 5.*/
|
||||
#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
|
||||
#define FW_PWR_STATE_RF_OFF 0
|
||||
|
||||
#define FW_PS_IS_ACK(x) ((x) & FW_PS_ACK)
|
||||
|
||||
#define IS_IN_LOW_POWER_STATE_92E(__state) \
|
||||
(FW_PS_STATE(__state) == FW_PS_CLOCK_OFF)
|
||||
|
||||
#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
|
||||
#define FW_PWR_STATE_RF_OFF 0
|
||||
|
||||
struct rtl92c_firmware_header {
|
||||
u16 signature;
|
||||
u8 category;
|
||||
u8 function;
|
||||
u16 version;
|
||||
u8 subversion;
|
||||
u8 rsvd1;
|
||||
u8 month;
|
||||
u8 date;
|
||||
u8 hour;
|
||||
u8 minute;
|
||||
u16 ramcodesize;
|
||||
u16 rsvd2;
|
||||
u32 svnindex;
|
||||
u32 rsvd3;
|
||||
u32 rsvd4;
|
||||
u32 rsvd5;
|
||||
};
|
||||
|
||||
enum rtl8192e_h2c_cmd {
|
||||
H2C_92E_RSVDPAGE = 0,
|
||||
H2C_92E_MSRRPT = 1,
|
||||
H2C_92E_SCAN = 2,
|
||||
H2C_92E_KEEP_ALIVE_CTRL = 3,
|
||||
H2C_92E_DISCONNECT_DECISION = 4,
|
||||
#if (USE_OLD_WOWLAN_DEBUG_FW == 1)
|
||||
H2C_92E_WO_WLAN = 5,
|
||||
#endif
|
||||
H2C_92E_INIT_OFFLOAD = 6,
|
||||
#if (USE_OLD_WOWLAN_DEBUG_FW == 1)
|
||||
H2C_92E_REMOTE_WAKE_CTRL = 7,
|
||||
#endif
|
||||
H2C_92E_AP_OFFLOAD = 8,
|
||||
H2C_92E_BCN_RSVDPAGE = 9,
|
||||
H2C_92E_PROBERSP_RSVDPAGE = 10,
|
||||
|
||||
H2C_92E_SETPWRMODE = 0x20,
|
||||
H2C_92E_PS_TUNING_PARA = 0x21,
|
||||
H2C_92E_PS_TUNING_PARA2 = 0x22,
|
||||
H2C_92E_PS_LPS_PARA = 0x23,
|
||||
H2C_92E_P2P_PS_OFFLOAD = 024,
|
||||
|
||||
#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
|
||||
H2C_92E_WO_WLAN = 0x80,
|
||||
H2C_92E_REMOTE_WAKE_CTRL = 0x81,
|
||||
H2C_92E_AOAC_GLOBAL_INFO = 0x82,
|
||||
H2C_92E_AOAC_RSVDPAGE = 0x83,
|
||||
#endif
|
||||
H2C_92E_RA_MASK = 0x40,
|
||||
H2C_92E_RSSI_REPORT = 0x42,
|
||||
H2C_92E_SELECTIVE_SUSPEND_ROF_CMD,
|
||||
H2C_92E_P2P_PS_MODE,
|
||||
H2C_92E_PSD_RESULT,
|
||||
/*Not defined CTW CMD for P2P yet*/
|
||||
H2C_92E_P2P_PS_CTW_CMD,
|
||||
MAX_92E_H2CCMD
|
||||
};
|
||||
|
||||
enum rtl8192e_c2h_evt {
|
||||
C2H_8192E_DBG = 0,
|
||||
C2H_8192E_LB = 1,
|
||||
C2H_8192E_TXBF = 2,
|
||||
C2H_8192E_TX_REPORT = 3,
|
||||
C2H_8192E_BT_INFO = 9,
|
||||
C2H_8192E_BT_MP = 11,
|
||||
C2H_8192E_RA_RPT = 12,
|
||||
MAX_8192E_C2HEVENT
|
||||
};
|
||||
|
||||
#define pagenum_128(_len) \
|
||||
(u32)(((_len) >> 7) + ((_len) & 0x7F ? 1 : 0))
|
||||
|
||||
#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_RLBM(__cmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 4, __val)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__cmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+1, 4, 4, __val)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(__cmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __val)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__cmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+3, 0, 8, __val)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__cmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE((__cmd)+4, 0, 8, __val)
|
||||
#define GET_92E_H2CCMD_PWRMODE_PARM_MODE(__cmd) \
|
||||
LE_BITS_TO_1BYTE(__cmd, 0, 8)
|
||||
|
||||
#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
|
||||
|
||||
/* _MEDIA_STATUS_RPT_PARM_CMD1 */
|
||||
#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__cmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __val)
|
||||
#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__cmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __val)
|
||||
#define SET_H2CCMD_MSRRPT_PARM_MACID(__cmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd+1, 0, 8, __val)
|
||||
#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__cmd, __val) \
|
||||
SET_BITS_TO_LE_1BYTE(__cmd+2, 0, 8, __val)
|
||||
|
||||
int rtl92ee_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw);
|
||||
void rtl92ee_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
|
||||
u32 cmd_len, u8 *cmdbuffer);
|
||||
void rtl92ee_firmware_selfreset(struct ieee80211_hw *hw);
|
||||
void rtl92ee_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
|
||||
void rtl92ee_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus);
|
||||
void rtl92ee_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
|
||||
void rtl92ee_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);
|
||||
void rtl92ee_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 len);
|
||||
|
||||
#endif
|
||||
2569
drivers/net/wireless/rtlwifi/rtl8192ee/hw.c
Normal file
2569
drivers/net/wireless/rtlwifi/rtl8192ee/hw.c
Normal file
File diff suppressed because it is too large
Load Diff
62
drivers/net/wireless/rtlwifi/rtl8192ee/hw.h
Normal file
62
drivers/net/wireless/rtlwifi/rtl8192ee/hw.h
Normal file
@ -0,0 +1,62 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL92E_HW_H__
|
||||
#define __RTL92E_HW_H__
|
||||
|
||||
void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
|
||||
void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw);
|
||||
void rtl92ee_interrupt_recognized(struct ieee80211_hw *hw,
|
||||
u32 *p_inta, u32 *p_intb);
|
||||
int rtl92ee_hw_init(struct ieee80211_hw *hw);
|
||||
void rtl92ee_card_disable(struct ieee80211_hw *hw);
|
||||
void rtl92ee_enable_interrupt(struct ieee80211_hw *hw);
|
||||
void rtl92ee_disable_interrupt(struct ieee80211_hw *hw);
|
||||
int rtl92ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
|
||||
void rtl92ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
|
||||
void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci);
|
||||
void rtl92ee_set_beacon_related_registers(struct ieee80211_hw *hw);
|
||||
void rtl92ee_set_beacon_interval(struct ieee80211_hw *hw);
|
||||
void rtl92ee_update_interrupt_mask(struct ieee80211_hw *hw,
|
||||
u32 add_msr, u32 rm_msr);
|
||||
void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
|
||||
void rtl92ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
|
||||
struct ieee80211_sta *sta, u8 rssi_level);
|
||||
void rtl92ee_update_channel_access_setting(struct ieee80211_hw *hw);
|
||||
bool rtl92ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
|
||||
void rtl92ee_enable_hw_security_config(struct ieee80211_hw *hw);
|
||||
void rtl92ee_set_key(struct ieee80211_hw *hw, u32 key_index,
|
||||
u8 *p_macaddr, bool is_group, u8 enc_algo,
|
||||
bool is_wepkey, bool clear_all);
|
||||
void rtl92ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
|
||||
bool autoload_fail, u8 *hwinfo);
|
||||
void rtl92ee_bt_reg_init(struct ieee80211_hw *hw);
|
||||
void rtl92ee_bt_hw_init(struct ieee80211_hw *hw);
|
||||
void rtl92ee_suspend(struct ieee80211_hw *hw);
|
||||
void rtl92ee_resume(struct ieee80211_hw *hw);
|
||||
void rtl92ee_allow_all_destaddr(struct ieee80211_hw *hw, bool allow_all_da,
|
||||
bool write_into_reg);
|
||||
void rtl92ee_fw_clk_off_timer_callback(unsigned long data);
|
||||
#endif
|
||||
145
drivers/net/wireless/rtlwifi/rtl8192ee/led.c
Normal file
145
drivers/net/wireless/rtlwifi/rtl8192ee/led.c
Normal file
@ -0,0 +1,145 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "../wifi.h"
|
||||
#include "../pci.h"
|
||||
#include "reg.h"
|
||||
#include "led.h"
|
||||
|
||||
static void _rtl92ee_init_led(struct ieee80211_hw *hw,
|
||||
struct rtl_led *pled, enum rtl_led_pin ledpin)
|
||||
{
|
||||
pled->hw = hw;
|
||||
pled->ledpin = ledpin;
|
||||
pled->ledon = false;
|
||||
}
|
||||
|
||||
void rtl92ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
|
||||
{
|
||||
u32 ledcfg;
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
|
||||
"LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
|
||||
|
||||
switch (pled->ledpin) {
|
||||
case LED_PIN_GPIO0:
|
||||
break;
|
||||
case LED_PIN_LED0:
|
||||
ledcfg = rtl_read_dword(rtlpriv , REG_GPIO_PIN_CTRL);
|
||||
ledcfg &= ~BIT(13);
|
||||
ledcfg |= BIT(21);
|
||||
ledcfg &= ~BIT(29);
|
||||
|
||||
rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, ledcfg);
|
||||
|
||||
break;
|
||||
case LED_PIN_LED1:
|
||||
|
||||
break;
|
||||
default:
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
|
||||
"switch case not process\n");
|
||||
break;
|
||||
}
|
||||
pled->ledon = true;
|
||||
}
|
||||
|
||||
void rtl92ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
u32 ledcfg;
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
|
||||
"LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
|
||||
|
||||
switch (pled->ledpin) {
|
||||
case LED_PIN_GPIO0:
|
||||
break;
|
||||
case LED_PIN_LED0:
|
||||
|
||||
ledcfg = rtl_read_dword(rtlpriv , REG_GPIO_PIN_CTRL);
|
||||
ledcfg |= ~BIT(21);
|
||||
ledcfg &= ~BIT(29);
|
||||
rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, ledcfg);
|
||||
|
||||
break;
|
||||
case LED_PIN_LED1:
|
||||
|
||||
break;
|
||||
default:
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
|
||||
"switch case not process\n");
|
||||
break;
|
||||
}
|
||||
pled->ledon = false;
|
||||
}
|
||||
|
||||
void rtl92ee_init_sw_leds(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
|
||||
|
||||
_rtl92ee_init_led(hw, &pcipriv->ledctl.sw_led0, LED_PIN_LED0);
|
||||
_rtl92ee_init_led(hw, &pcipriv->ledctl.sw_led1, LED_PIN_LED1);
|
||||
}
|
||||
|
||||
static void _rtl92ee_sw_led_control(struct ieee80211_hw *hw,
|
||||
enum led_ctl_mode ledaction)
|
||||
{
|
||||
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
|
||||
struct rtl_led *pLed0 = &pcipriv->ledctl.sw_led0;
|
||||
|
||||
switch (ledaction) {
|
||||
case LED_CTL_POWER_ON:
|
||||
case LED_CTL_LINK:
|
||||
case LED_CTL_NO_LINK:
|
||||
rtl92ee_sw_led_on(hw, pLed0);
|
||||
break;
|
||||
case LED_CTL_POWER_OFF:
|
||||
rtl92ee_sw_led_off(hw, pLed0);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rtl92ee_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
|
||||
|
||||
if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
|
||||
(ledaction == LED_CTL_TX ||
|
||||
ledaction == LED_CTL_RX ||
|
||||
ledaction == LED_CTL_SITE_SURVEY ||
|
||||
ledaction == LED_CTL_LINK ||
|
||||
ledaction == LED_CTL_NO_LINK ||
|
||||
ledaction == LED_CTL_START_TO_LINK ||
|
||||
ledaction == LED_CTL_POWER_ON)) {
|
||||
return;
|
||||
}
|
||||
RT_TRACE(rtlpriv, COMP_LED, DBG_TRACE, "ledaction %d,\n", ledaction);
|
||||
_rtl92ee_sw_led_control(hw, ledaction);
|
||||
}
|
||||
34
drivers/net/wireless/rtlwifi/rtl8192ee/led.h
Normal file
34
drivers/net/wireless/rtlwifi/rtl8192ee/led.h
Normal file
@ -0,0 +1,34 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL92E_LED_H__
|
||||
#define __RTL92E_LED_H__
|
||||
|
||||
void rtl92ee_init_sw_leds(struct ieee80211_hw *hw);
|
||||
void rtl92ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
|
||||
void rtl92ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
|
||||
void rtl92ee_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
|
||||
|
||||
#endif
|
||||
3219
drivers/net/wireless/rtlwifi/rtl8192ee/phy.c
Normal file
3219
drivers/net/wireless/rtlwifi/rtl8192ee/phy.c
Normal file
File diff suppressed because it is too large
Load Diff
153
drivers/net/wireless/rtlwifi/rtl8192ee/phy.h
Normal file
153
drivers/net/wireless/rtlwifi/rtl8192ee/phy.h
Normal file
@ -0,0 +1,153 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL92E_PHY_H__
|
||||
#define __RTL92E_PHY_H__
|
||||
|
||||
/* MAX_TX_COUNT must always set to 4, otherwise read efuse table sequence
|
||||
* will be wrong.
|
||||
*/
|
||||
#define MAX_TX_COUNT 4
|
||||
#define TX_1S 0
|
||||
#define TX_2S 1
|
||||
#define TX_3S 2
|
||||
#define TX_4S 3
|
||||
|
||||
#define MAX_POWER_INDEX 0x3f
|
||||
|
||||
#define MAX_PRECMD_CNT 16
|
||||
#define MAX_RFDEPENDCMD_CNT 16
|
||||
#define MAX_POSTCMD_CNT 16
|
||||
|
||||
#define MAX_DOZE_WAITING_TIMES_9x 64
|
||||
|
||||
#define RT_CANNOT_IO(hw) false
|
||||
#define HIGHPOWER_RADIOA_ARRAYLEN 22
|
||||
|
||||
#define IQK_ADDA_REG_NUM 16
|
||||
#define IQK_MAC_REG_NUM 4
|
||||
#define IQK_BB_REG_NUM 9
|
||||
#define MAX_TOLERANCE 5
|
||||
#define IQK_DELAY_TIME 10
|
||||
#define index_mapping_NUM 15
|
||||
|
||||
#define APK_BB_REG_NUM 5
|
||||
#define APK_AFE_REG_NUM 16
|
||||
#define APK_CURVE_REG_NUM 4
|
||||
#define PATH_NUM 2
|
||||
|
||||
#define LOOP_LIMIT 5
|
||||
#define MAX_STALL_TIME 50
|
||||
#define ANTENNADIVERSITYVALUE 0x80
|
||||
#define MAX_TXPWR_IDX_NMODE_92S 63
|
||||
#define RESET_CNT_LIMIT 3
|
||||
|
||||
#define RF6052_MAX_PATH 2
|
||||
|
||||
#define CT_OFFSET_MAC_ADDR 0X16
|
||||
|
||||
#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
|
||||
#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
|
||||
#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
|
||||
#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
|
||||
#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
|
||||
|
||||
#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
|
||||
#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
|
||||
|
||||
#define CT_OFFSET_CHANNEL_PLAH 0x75
|
||||
#define CT_OFFSET_THERMAL_METER 0x78
|
||||
#define CT_OFFSET_RF_OPTION 0x79
|
||||
#define CT_OFFSET_VERSION 0x7E
|
||||
#define CT_OFFSET_CUSTOMER_ID 0x7F
|
||||
|
||||
#define RTL92C_MAX_PATH_NUM 2
|
||||
|
||||
enum swchnlcmd_id {
|
||||
CMDID_END,
|
||||
CMDID_SET_TXPOWEROWER_LEVEL,
|
||||
CMDID_BBREGWRITE10,
|
||||
CMDID_WRITEPORT_ULONG,
|
||||
CMDID_WRITEPORT_USHORT,
|
||||
CMDID_WRITEPORT_UCHAR,
|
||||
CMDID_RF_WRITEREG,
|
||||
};
|
||||
|
||||
struct swchnlcmd {
|
||||
enum swchnlcmd_id cmdid;
|
||||
u32 para1;
|
||||
u32 para2;
|
||||
u32 msdelay;
|
||||
};
|
||||
|
||||
enum baseband_config_type {
|
||||
BASEBAND_CONFIG_PHY_REG = 0,
|
||||
BASEBAND_CONFIG_AGC_TAB = 1,
|
||||
};
|
||||
|
||||
enum ant_div_type {
|
||||
NO_ANTDIV = 0xFF,
|
||||
CG_TRX_HW_ANTDIV = 0x01,
|
||||
CGCS_RX_HW_ANTDIV = 0x02,
|
||||
FIXED_HW_ANTDIV = 0x03,
|
||||
CG_TRX_SMART_ANTDIV = 0x04,
|
||||
CGCS_RX_SW_ANTDIV = 0x05,
|
||||
};
|
||||
|
||||
u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw,
|
||||
u32 regaddr, u32 bitmask);
|
||||
void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw,
|
||||
u32 regaddr, u32 bitmask, u32 data);
|
||||
u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw,
|
||||
enum radio_path rfpath, u32 regaddr,
|
||||
u32 bitmask);
|
||||
void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw,
|
||||
enum radio_path rfpath, u32 regaddr,
|
||||
u32 bitmask, u32 data);
|
||||
bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw);
|
||||
bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw);
|
||||
bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw);
|
||||
void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
|
||||
void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw,
|
||||
long *powerlevel);
|
||||
void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
|
||||
void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw,
|
||||
u8 operation);
|
||||
void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
|
||||
void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw,
|
||||
enum nl80211_channel_type ch_type);
|
||||
void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw);
|
||||
u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw);
|
||||
void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
|
||||
void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
|
||||
void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw);
|
||||
void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
|
||||
bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
|
||||
enum radio_path rfpath);
|
||||
bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
|
||||
bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
|
||||
enum rf_pwrstate rfpwr_state);
|
||||
|
||||
#endif
|
||||
112
drivers/net/wireless/rtlwifi/rtl8192ee/pwrseq.c
Normal file
112
drivers/net/wireless/rtlwifi/rtl8192ee/pwrseq.c
Normal file
@ -0,0 +1,112 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "pwrseq.h"
|
||||
|
||||
/* drivers should parse below arrays and do the corresponding actions */
|
||||
|
||||
/*3 Power on Array*/
|
||||
struct wlan_pwr_cfg rtl8192E_power_on_flow
|
||||
[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS] = {
|
||||
RTL8192E_TRANS_CARDEMU_TO_ACT
|
||||
RTL8192E_TRANS_END
|
||||
};
|
||||
|
||||
/*3Radio off GPIO Array */
|
||||
struct wlan_pwr_cfg rtl8192E_radio_off_flow
|
||||
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS
|
||||
+ RTL8192E_TRANS_END_STEPS] = {
|
||||
RTL8192E_TRANS_ACT_TO_CARDEMU
|
||||
RTL8192E_TRANS_END
|
||||
};
|
||||
|
||||
/*3Card Disable Array*/
|
||||
struct wlan_pwr_cfg rtl8192E_card_disable_flow
|
||||
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS] = {
|
||||
RTL8192E_TRANS_ACT_TO_CARDEMU
|
||||
RTL8192E_TRANS_CARDEMU_TO_CARDDIS
|
||||
RTL8192E_TRANS_END
|
||||
};
|
||||
|
||||
/*3 Card Enable Array*/
|
||||
struct wlan_pwr_cfg rtl8192E_card_enable_flow
|
||||
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS] = {
|
||||
RTL8192E_TRANS_CARDDIS_TO_CARDEMU
|
||||
RTL8192E_TRANS_CARDEMU_TO_ACT
|
||||
RTL8192E_TRANS_END
|
||||
};
|
||||
|
||||
/*3Suspend Array*/
|
||||
struct wlan_pwr_cfg rtl8192E_suspend_flow
|
||||
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS] = {
|
||||
RTL8192E_TRANS_ACT_TO_CARDEMU
|
||||
RTL8192E_TRANS_CARDEMU_TO_SUS
|
||||
RTL8192E_TRANS_END
|
||||
};
|
||||
|
||||
/*3 Resume Array*/
|
||||
struct wlan_pwr_cfg rtl8192E_resume_flow
|
||||
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS] = {
|
||||
RTL8192E_TRANS_SUS_TO_CARDEMU
|
||||
RTL8192E_TRANS_CARDEMU_TO_ACT
|
||||
RTL8192E_TRANS_END
|
||||
};
|
||||
|
||||
/*3HWPDN Array*/
|
||||
struct wlan_pwr_cfg rtl8192E_hwpdn_flow
|
||||
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS] = {
|
||||
RTL8192E_TRANS_ACT_TO_CARDEMU
|
||||
RTL8192E_TRANS_CARDEMU_TO_PDN
|
||||
RTL8192E_TRANS_END
|
||||
};
|
||||
|
||||
/*3 Enter LPS */
|
||||
struct wlan_pwr_cfg rtl8192E_enter_lps_flow
|
||||
[RTL8192E_TRANS_ACT_TO_LPS_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS] = {
|
||||
/*FW behavior*/
|
||||
RTL8192E_TRANS_ACT_TO_LPS
|
||||
RTL8192E_TRANS_END
|
||||
};
|
||||
|
||||
/*3 Leave LPS */
|
||||
struct wlan_pwr_cfg rtl8192E_leave_lps_flow
|
||||
[RTL8192E_TRANS_LPS_TO_ACT_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS] = {
|
||||
/*FW behavior*/
|
||||
RTL8192E_TRANS_LPS_TO_ACT
|
||||
RTL8192E_TRANS_END
|
||||
};
|
||||
340
drivers/net/wireless/rtlwifi/rtl8192ee/pwrseq.h
Normal file
340
drivers/net/wireless/rtlwifi/rtl8192ee/pwrseq.h
Normal file
@ -0,0 +1,340 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL92E_PWRSEQ_H__
|
||||
#define __RTL92E_PWRSEQ_H__
|
||||
|
||||
#include "../pwrseqcmd.h"
|
||||
/**
|
||||
* Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd
|
||||
* There are 6 HW Power States:
|
||||
* 0: POFF--Power Off
|
||||
* 1: PDN--Power Down
|
||||
* 2: CARDEMU--Card Emulation
|
||||
* 3: ACT--Active Mode
|
||||
* 4: LPS--Low Power State
|
||||
* 5: SUS--Suspend
|
||||
*
|
||||
* The transision from different states are defined below
|
||||
* TRANS_CARDEMU_TO_ACT
|
||||
* TRANS_ACT_TO_CARDEMU
|
||||
* TRANS_CARDEMU_TO_SUS
|
||||
* TRANS_SUS_TO_CARDEMU
|
||||
* TRANS_CARDEMU_TO_PDN
|
||||
* TRANS_ACT_TO_LPS
|
||||
* TRANS_LPS_TO_ACT
|
||||
*
|
||||
* TRANS_END
|
||||
* PWR SEQ Version: rtl8192E_PwrSeq_V09.h
|
||||
*/
|
||||
|
||||
#define RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS 18
|
||||
#define RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS 18
|
||||
#define RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS 18
|
||||
#define RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS 18
|
||||
#define RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS 18
|
||||
#define RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS 18
|
||||
#define RTL8192E_TRANS_ACT_TO_LPS_STEPS 23
|
||||
#define RTL8192E_TRANS_LPS_TO_ACT_STEPS 23
|
||||
#define RTL8192E_TRANS_END_STEPS 1
|
||||
|
||||
#define RTL8192E_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* comments here */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
|
||||
/* disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
|
||||
/* disable SW LPS 0x04[10]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
|
||||
/* disable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
|
||||
/* wait till 0x04[17] = 1 power ready*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
|
||||
/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
|
||||
/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
|
||||
/**/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(0), 0},
|
||||
|
||||
#define RTL8192E_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* comments here */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
|
||||
/*0x1F[7:0] = 0 turn off RF*/ \
|
||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
|
||||
/*0x4C[23]=0x4E[7]=0, switch DPDT_SEL_P output from register 0x65[2] */\
|
||||
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
|
||||
/*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
|
||||
/*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), 0},
|
||||
|
||||
#define RTL8192E_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* comments here */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
|
||||
/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},\
|
||||
/*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
|
||||
PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
|
||||
PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
|
||||
/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
|
||||
/*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
|
||||
/*wait power state to suspend*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
|
||||
|
||||
#define RTL8192E_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* comments here */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
|
||||
/*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \
|
||||
/*wait power state to suspend*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
|
||||
/*0x04[12:11] = 2b'01enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
|
||||
|
||||
#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* comments here */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
|
||||
/*0x07=0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x20}, \
|
||||
/*Unlock small LDO Register*/ \
|
||||
{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
|
||||
/*Disable small LDO*/ \
|
||||
{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
|
||||
/*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
|
||||
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
|
||||
PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
|
||||
/*0x04[10] = 1, enable SW LPS*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
|
||||
/*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
|
||||
/*wait power state to suspend*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
|
||||
|
||||
#define RTL8192E_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* comments here */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
|
||||
/*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \
|
||||
/*wait power state to suspend*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
|
||||
/*Enable small LDO*/ \
|
||||
{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
|
||||
/*Lock small LDO Register*/ \
|
||||
{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
|
||||
/*0x04[12:11] = 2b'01enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
|
||||
|
||||
#define RTL8192E_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* comments here */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
|
||||
/* 0x04[16] = 0*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
|
||||
/* 0x04[15] = 1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), BIT(7)},
|
||||
|
||||
#define RTL8192E_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* comments here */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
|
||||
/* 0x04[15] = 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},
|
||||
|
||||
#define RTL8192E_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* comments here */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
|
||||
/*PCIe DMA stop*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
|
||||
/*Tx Pause*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
|
||||
/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
|
||||
/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
|
||||
/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
|
||||
/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
|
||||
/*CCK and OFDM are disabled,and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
|
||||
/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
|
||||
/*Whole BB is reset*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
|
||||
/*Reset MAC TRX*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x03}, \
|
||||
/*check if removed later*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
|
||||
/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x00}, \
|
||||
/*Respond TxOK to scheduler*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(5), BIT(5)},
|
||||
|
||||
#define RTL8192E_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* comments here */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
|
||||
/*SDIO RPWM, For Repeatly In and out, Taggle bit should be changed*/\
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||||
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, 0xFF, 0x84}, \
|
||||
/*USB RPWM*/ \
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84}, \
|
||||
/*PCIe RPWM*/ \
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84}, \
|
||||
/*Delay*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
|
||||
/*0x08[4] = 0 switch TSF to 40M*/ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4), 0}, \
|
||||
/*Polling 0x109[7]=0 TSF in 40M*/ \
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(7), 0}, \
|
||||
/*0x101[1] = 1*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
|
||||
/*0x100[7:0] = 0xFF enable WMAC TRX*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
|
||||
/* 0x02[1:0] = 2b'11 enable BB macro*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},\
|
||||
/*0x522 = 0*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
|
||||
/*Clear ISR*/ \
|
||||
{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},
|
||||
|
||||
#define RTL8192E_TRANS_END \
|
||||
/* format */ \
|
||||
/* comments here */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||||
0, PWR_CMD_END, 0, 0},
|
||||
|
||||
extern struct wlan_pwr_cfg rtl8192E_power_on_flow
|
||||
[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8192E_radio_off_flow
|
||||
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8192E_card_disable_flow
|
||||
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8192E_card_enable_flow
|
||||
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8192E_suspend_flow
|
||||
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8192E_resume_flow
|
||||
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8192E_hwpdn_flow
|
||||
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||||
RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8192E_enter_lps_flow
|
||||
[RTL8192E_TRANS_ACT_TO_LPS_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS];
|
||||
extern struct wlan_pwr_cfg rtl8192E_leave_lps_flow
|
||||
[RTL8192E_TRANS_LPS_TO_ACT_STEPS +
|
||||
RTL8192E_TRANS_END_STEPS];
|
||||
|
||||
/* RTL8192EE Power Configuration CMDs for PCIe interface */
|
||||
#define RTL8192E_NIC_PWR_ON_FLOW rtl8192E_power_on_flow
|
||||
#define RTL8192E_NIC_RF_OFF_FLOW rtl8192E_radio_off_flow
|
||||
#define RTL8192E_NIC_DISABLE_FLOW rtl8192E_card_disable_flow
|
||||
#define RTL8192E_NIC_ENABLE_FLOW rtl8192E_card_enable_flow
|
||||
#define RTL8192E_NIC_SUSPEND_FLOW rtl8192E_suspend_flow
|
||||
#define RTL8192E_NIC_RESUME_FLOW rtl8192E_resume_flow
|
||||
#define RTL8192E_NIC_PDN_FLOW rtl8192E_hwpdn_flow
|
||||
#define RTL8192E_NIC_LPS_ENTER_FLOW rtl8192E_enter_lps_flow
|
||||
#define RTL8192E_NIC_LPS_LEAVE_FLOW rtl8192E_leave_lps_flow
|
||||
|
||||
#endif
|
||||
2231
drivers/net/wireless/rtlwifi/rtl8192ee/reg.h
Normal file
2231
drivers/net/wireless/rtlwifi/rtl8192ee/reg.h
Normal file
File diff suppressed because it is too large
Load Diff
152
drivers/net/wireless/rtlwifi/rtl8192ee/rf.c
Normal file
152
drivers/net/wireless/rtlwifi/rtl8192ee/rf.c
Normal file
@ -0,0 +1,152 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "../wifi.h"
|
||||
#include "reg.h"
|
||||
#include "def.h"
|
||||
#include "phy.h"
|
||||
#include "rf.h"
|
||||
#include "dm.h"
|
||||
|
||||
static bool _rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
|
||||
|
||||
void rtl92ee_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_phy *rtlphy = &rtlpriv->phy;
|
||||
|
||||
switch (bandwidth) {
|
||||
case HT_CHANNEL_WIDTH_20:
|
||||
rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
|
||||
0xfffff3ff) | BIT(10) | BIT(11));
|
||||
rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
|
||||
rtlphy->rfreg_chnlval[0]);
|
||||
rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
|
||||
rtlphy->rfreg_chnlval[0]);
|
||||
break;
|
||||
case HT_CHANNEL_WIDTH_20_40:
|
||||
rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
|
||||
0xfffff3ff) | BIT(10));
|
||||
rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
|
||||
rtlphy->rfreg_chnlval[0]);
|
||||
rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
|
||||
rtlphy->rfreg_chnlval[0]);
|
||||
break;
|
||||
default:
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
|
||||
"unknown bandwidth: %#X\n", bandwidth);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
bool rtl92ee_phy_rf6052_config(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_phy *rtlphy = &rtlpriv->phy;
|
||||
|
||||
if (rtlphy->rf_type == RF_1T1R)
|
||||
rtlphy->num_total_rfpath = 1;
|
||||
else
|
||||
rtlphy->num_total_rfpath = 2;
|
||||
|
||||
return _rtl92ee_phy_rf6052_config_parafile(hw);
|
||||
}
|
||||
|
||||
static bool _rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_phy *rtlphy = &rtlpriv->phy;
|
||||
u32 u4_regvalue = 0;
|
||||
u8 rfpath;
|
||||
bool rtstatus = true;
|
||||
struct bb_reg_def *pphyreg;
|
||||
|
||||
for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
|
||||
pphyreg = &rtlphy->phyreg_def[rfpath];
|
||||
|
||||
switch (rfpath) {
|
||||
case RF90_PATH_A:
|
||||
case RF90_PATH_C:
|
||||
u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
|
||||
BRFSI_RFENV);
|
||||
break;
|
||||
case RF90_PATH_B:
|
||||
case RF90_PATH_D:
|
||||
u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
|
||||
BRFSI_RFENV << 16);
|
||||
break;
|
||||
}
|
||||
|
||||
rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
|
||||
udelay(1);
|
||||
|
||||
rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
|
||||
udelay(1);
|
||||
|
||||
rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
|
||||
B3WIREADDREAALENGTH, 0x0);
|
||||
udelay(1);
|
||||
|
||||
rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
|
||||
udelay(1);
|
||||
|
||||
switch (rfpath) {
|
||||
case RF90_PATH_A:
|
||||
rtstatus = rtl92ee_phy_config_rf_with_headerfile(hw,
|
||||
(enum radio_path)rfpath);
|
||||
break;
|
||||
case RF90_PATH_B:
|
||||
rtstatus = rtl92ee_phy_config_rf_with_headerfile(hw,
|
||||
(enum radio_path)rfpath);
|
||||
break;
|
||||
case RF90_PATH_C:
|
||||
break;
|
||||
case RF90_PATH_D:
|
||||
break;
|
||||
}
|
||||
|
||||
switch (rfpath) {
|
||||
case RF90_PATH_A:
|
||||
case RF90_PATH_C:
|
||||
rtl_set_bbreg(hw, pphyreg->rfintfs,
|
||||
BRFSI_RFENV, u4_regvalue);
|
||||
break;
|
||||
case RF90_PATH_B:
|
||||
case RF90_PATH_D:
|
||||
rtl_set_bbreg(hw, pphyreg->rfintfs,
|
||||
BRFSI_RFENV << 16, u4_regvalue);
|
||||
break;
|
||||
}
|
||||
|
||||
if (!rtstatus) {
|
||||
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
|
||||
"Radio[%d] Fail!!", rfpath);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
|
||||
return rtstatus;
|
||||
}
|
||||
36
drivers/net/wireless/rtlwifi/rtl8192ee/rf.h
Normal file
36
drivers/net/wireless/rtlwifi/rtl8192ee/rf.h
Normal file
@ -0,0 +1,36 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL92E_RF_H__
|
||||
#define __RTL92E_RF_H__
|
||||
|
||||
#define RF6052_MAX_TX_PWR 0x3F
|
||||
#define RF6052_MAX_REG 0x3F
|
||||
|
||||
void rtl92ee_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
|
||||
u8 bandwidth);
|
||||
bool rtl92ee_phy_rf6052_config(struct ieee80211_hw *hw);
|
||||
|
||||
#endif
|
||||
399
drivers/net/wireless/rtlwifi/rtl8192ee/sw.c
Normal file
399
drivers/net/wireless/rtlwifi/rtl8192ee/sw.c
Normal file
@ -0,0 +1,399 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "../wifi.h"
|
||||
#include "../core.h"
|
||||
#include "../pci.h"
|
||||
#include "reg.h"
|
||||
#include "def.h"
|
||||
#include "phy.h"
|
||||
#include "dm.h"
|
||||
#include "hw.h"
|
||||
#include "sw.h"
|
||||
#include "fw.h"
|
||||
#include "trx.h"
|
||||
#include "led.h"
|
||||
#include "table.h"
|
||||
|
||||
#include "../btcoexist/rtl_btc.h"
|
||||
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
static void rtl92ee_init_aspm_vars(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
|
||||
|
||||
/*close ASPM for AMD defaultly */
|
||||
rtlpci->const_amdpci_aspm = 0;
|
||||
|
||||
/**
|
||||
* ASPM PS mode.
|
||||
* 0 - Disable ASPM,
|
||||
* 1 - Enable ASPM without Clock Req,
|
||||
* 2 - Enable ASPM with Clock Req,
|
||||
* 3 - Alwyas Enable ASPM with Clock Req,
|
||||
* 4 - Always Enable ASPM without Clock Req.
|
||||
* set defult to RTL8192CE:3 RTL8192E:2
|
||||
*/
|
||||
rtlpci->const_pci_aspm = 3;
|
||||
|
||||
/*Setting for PCI-E device */
|
||||
rtlpci->const_devicepci_aspm_setting = 0x03;
|
||||
|
||||
/*Setting for PCI-E bridge */
|
||||
rtlpci->const_hostpci_aspm_setting = 0x02;
|
||||
|
||||
/**
|
||||
* In Hw/Sw Radio Off situation.
|
||||
* 0 - Default,
|
||||
* 1 - From ASPM setting without low Mac Pwr,
|
||||
* 2 - From ASPM setting with low Mac Pwr,
|
||||
* 3 - Bus D3
|
||||
* set default to RTL8192CE:0 RTL8192SE:2
|
||||
*/
|
||||
rtlpci->const_hwsw_rfoff_d3 = 0;
|
||||
|
||||
/**
|
||||
* This setting works for those device with
|
||||
* backdoor ASPM setting such as EPHY setting.
|
||||
* 0 - Not support ASPM,
|
||||
* 1 - Support ASPM,
|
||||
* 2 - According to chipset.
|
||||
*/
|
||||
rtlpci->const_support_pciaspm = 1;
|
||||
}
|
||||
|
||||
int rtl92ee_init_sw_vars(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
|
||||
int err = 0;
|
||||
|
||||
rtl92ee_bt_reg_init(hw);
|
||||
rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
|
||||
rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
|
||||
|
||||
rtlpriv->dm.dm_initialgain_enable = 1;
|
||||
rtlpriv->dm.dm_flag = 0;
|
||||
rtlpriv->dm.disable_framebursting = 0;
|
||||
rtlpci->transmit_config = CFENDFORM | BIT(15);
|
||||
|
||||
/*just 2.4G band*/
|
||||
rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
|
||||
rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
|
||||
rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
|
||||
|
||||
rtlpci->receive_config = (RCR_APPFCS |
|
||||
RCR_APP_MIC |
|
||||
RCR_APP_ICV |
|
||||
RCR_APP_PHYST_RXFF |
|
||||
RCR_HTC_LOC_CTRL |
|
||||
RCR_AMF |
|
||||
RCR_ACF |
|
||||
RCR_ADF |
|
||||
RCR_AICV |
|
||||
RCR_ACRC32 |
|
||||
RCR_AB |
|
||||
RCR_AM |
|
||||
RCR_APM |
|
||||
0);
|
||||
|
||||
rtlpci->irq_mask[0] = (u32)(IMR_PSTIMEOUT |
|
||||
IMR_C2HCMD |
|
||||
IMR_HIGHDOK |
|
||||
IMR_MGNTDOK |
|
||||
IMR_BKDOK |
|
||||
IMR_BEDOK |
|
||||
IMR_VIDOK |
|
||||
IMR_VODOK |
|
||||
IMR_RDU |
|
||||
IMR_ROK |
|
||||
0);
|
||||
rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);
|
||||
|
||||
/* for debug level */
|
||||
rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
|
||||
/* for LPS & IPS */
|
||||
rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
|
||||
rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
|
||||
rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
|
||||
rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
|
||||
if (rtlpriv->cfg->mod_params->disable_watchdog)
|
||||
pr_info("watchdog disabled\n");
|
||||
rtlpriv->psc.reg_fwctrl_lps = 3;
|
||||
rtlpriv->psc.reg_max_lps_awakeintvl = 5;
|
||||
/* for ASPM, you can close aspm through
|
||||
* set const_support_pciaspm = 0
|
||||
*/
|
||||
rtl92ee_init_aspm_vars(hw);
|
||||
|
||||
if (rtlpriv->psc.reg_fwctrl_lps == 1)
|
||||
rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
|
||||
else if (rtlpriv->psc.reg_fwctrl_lps == 2)
|
||||
rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
|
||||
else if (rtlpriv->psc.reg_fwctrl_lps == 3)
|
||||
rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
|
||||
|
||||
/* for early mode */
|
||||
rtlpriv->rtlhal.earlymode_enable = false;
|
||||
|
||||
/*low power */
|
||||
rtlpriv->psc.low_power_enable = false;
|
||||
|
||||
/* for firmware buf */
|
||||
rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
|
||||
if (!rtlpriv->rtlhal.pfirmware) {
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
|
||||
"Can't alloc buffer for fw\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* request fw */
|
||||
rtlpriv->cfg->fw_name = "rtlwifi/rtl8192eefw.bin";
|
||||
|
||||
rtlpriv->max_fw_size = 0x8000;
|
||||
pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
|
||||
err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
|
||||
rtlpriv->io.dev, GFP_KERNEL, hw,
|
||||
rtl_fw_cb);
|
||||
if (err) {
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
|
||||
"Failed to request firmware!\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
|
||||
if (rtlpriv->rtlhal.pfirmware) {
|
||||
vfree(rtlpriv->rtlhal.pfirmware);
|
||||
rtlpriv->rtlhal.pfirmware = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/* get bt coexist status */
|
||||
bool rtl92ee_get_btc_status(void)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static struct rtl_hal_ops rtl8192ee_hal_ops = {
|
||||
.init_sw_vars = rtl92ee_init_sw_vars,
|
||||
.deinit_sw_vars = rtl92ee_deinit_sw_vars,
|
||||
.read_eeprom_info = rtl92ee_read_eeprom_info,
|
||||
.interrupt_recognized = rtl92ee_interrupt_recognized,/*need check*/
|
||||
.hw_init = rtl92ee_hw_init,
|
||||
.hw_disable = rtl92ee_card_disable,
|
||||
.hw_suspend = rtl92ee_suspend,
|
||||
.hw_resume = rtl92ee_resume,
|
||||
.enable_interrupt = rtl92ee_enable_interrupt,
|
||||
.disable_interrupt = rtl92ee_disable_interrupt,
|
||||
.set_network_type = rtl92ee_set_network_type,
|
||||
.set_chk_bssid = rtl92ee_set_check_bssid,
|
||||
.set_qos = rtl92ee_set_qos,
|
||||
.set_bcn_reg = rtl92ee_set_beacon_related_registers,
|
||||
.set_bcn_intv = rtl92ee_set_beacon_interval,
|
||||
.update_interrupt_mask = rtl92ee_update_interrupt_mask,
|
||||
.get_hw_reg = rtl92ee_get_hw_reg,
|
||||
.set_hw_reg = rtl92ee_set_hw_reg,
|
||||
.update_rate_tbl = rtl92ee_update_hal_rate_tbl,
|
||||
.pre_fill_tx_bd_desc = rtl92ee_pre_fill_tx_bd_desc,
|
||||
.rx_desc_buff_remained_cnt = rtl92ee_rx_desc_buff_remained_cnt,
|
||||
.rx_check_dma_ok = rtl92ee_rx_check_dma_ok,
|
||||
.fill_tx_desc = rtl92ee_tx_fill_desc,
|
||||
.fill_tx_cmddesc = rtl92ee_tx_fill_cmddesc,
|
||||
.query_rx_desc = rtl92ee_rx_query_desc,
|
||||
.set_channel_access = rtl92ee_update_channel_access_setting,
|
||||
.radio_onoff_checking = rtl92ee_gpio_radio_on_off_checking,
|
||||
.set_bw_mode = rtl92ee_phy_set_bw_mode,
|
||||
.switch_channel = rtl92ee_phy_sw_chnl,
|
||||
.dm_watchdog = rtl92ee_dm_watchdog,
|
||||
.scan_operation_backup = rtl92ee_phy_scan_operation_backup,
|
||||
.set_rf_power_state = rtl92ee_phy_set_rf_power_state,
|
||||
.led_control = rtl92ee_led_control,
|
||||
.set_desc = rtl92ee_set_desc,
|
||||
.get_desc = rtl92ee_get_desc,
|
||||
.is_tx_desc_closed = rtl92ee_is_tx_desc_closed,
|
||||
.tx_polling = rtl92ee_tx_polling,
|
||||
.enable_hw_sec = rtl92ee_enable_hw_security_config,
|
||||
.set_key = rtl92ee_set_key,
|
||||
.init_sw_leds = rtl92ee_init_sw_leds,
|
||||
.get_bbreg = rtl92ee_phy_query_bb_reg,
|
||||
.set_bbreg = rtl92ee_phy_set_bb_reg,
|
||||
.get_rfreg = rtl92ee_phy_query_rf_reg,
|
||||
.set_rfreg = rtl92ee_phy_set_rf_reg,
|
||||
.fill_h2c_cmd = rtl92ee_fill_h2c_cmd,
|
||||
.get_btc_status = rtl92ee_get_btc_status,
|
||||
.rx_command_packet = rtl92ee_rx_command_packet,
|
||||
};
|
||||
|
||||
static struct rtl_mod_params rtl92ee_mod_params = {
|
||||
.sw_crypto = false,
|
||||
.inactiveps = false,
|
||||
.swctrl_lps = false,
|
||||
.fwctrl_lps = true,
|
||||
.msi_support = true,
|
||||
.debug = DBG_EMERG,
|
||||
};
|
||||
|
||||
static struct rtl_hal_cfg rtl92ee_hal_cfg = {
|
||||
.bar_id = 2,
|
||||
.write_readback = true,
|
||||
.name = "rtl92ee_pci",
|
||||
.fw_name = "rtlwifi/rtl8192eefw.bin",
|
||||
.ops = &rtl8192ee_hal_ops,
|
||||
.mod_params = &rtl92ee_mod_params,
|
||||
|
||||
.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
|
||||
.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
|
||||
.maps[SYS_CLK] = REG_SYS_CLKR,
|
||||
.maps[MAC_RCR_AM] = AM,
|
||||
.maps[MAC_RCR_AB] = AB,
|
||||
.maps[MAC_RCR_ACRC32] = ACRC32,
|
||||
.maps[MAC_RCR_ACF] = ACF,
|
||||
.maps[MAC_RCR_AAP] = AAP,
|
||||
.maps[MAC_HIMR] = REG_HIMR,
|
||||
.maps[MAC_HIMRE] = REG_HIMRE,
|
||||
|
||||
.maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
|
||||
|
||||
.maps[EFUSE_TEST] = REG_EFUSE_TEST,
|
||||
.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
|
||||
.maps[EFUSE_CLK] = 0,
|
||||
.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
|
||||
.maps[EFUSE_PWC_EV12V] = PWC_EV12V,
|
||||
.maps[EFUSE_FEN_ELDR] = FEN_ELDR,
|
||||
.maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
|
||||
.maps[EFUSE_ANA8M] = ANA8M,
|
||||
.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
|
||||
.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
|
||||
.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
|
||||
.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
|
||||
|
||||
.maps[RWCAM] = REG_CAMCMD,
|
||||
.maps[WCAMI] = REG_CAMWRITE,
|
||||
.maps[RCAMO] = REG_CAMREAD,
|
||||
.maps[CAMDBG] = REG_CAMDBG,
|
||||
.maps[SECR] = REG_SECCFG,
|
||||
.maps[SEC_CAM_NONE] = CAM_NONE,
|
||||
.maps[SEC_CAM_WEP40] = CAM_WEP40,
|
||||
.maps[SEC_CAM_TKIP] = CAM_TKIP,
|
||||
.maps[SEC_CAM_AES] = CAM_AES,
|
||||
.maps[SEC_CAM_WEP104] = CAM_WEP104,
|
||||
|
||||
.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
|
||||
.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
|
||||
.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
|
||||
.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
|
||||
.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
|
||||
.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
|
||||
.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
|
||||
.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
|
||||
.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
|
||||
.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
|
||||
.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
|
||||
.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
|
||||
.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
|
||||
|
||||
.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
|
||||
.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
|
||||
.maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
|
||||
.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
|
||||
.maps[RTL_IMR_RDU] = IMR_RDU,
|
||||
.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
|
||||
.maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
|
||||
.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
|
||||
.maps[RTL_IMR_TBDER] = IMR_TBDER,
|
||||
.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
|
||||
.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
|
||||
.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
|
||||
.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
|
||||
.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
|
||||
.maps[RTL_IMR_VODOK] = IMR_VODOK,
|
||||
.maps[RTL_IMR_ROK] = IMR_ROK,
|
||||
.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
|
||||
|
||||
.maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
|
||||
.maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
|
||||
.maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
|
||||
.maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
|
||||
.maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
|
||||
.maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
|
||||
.maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
|
||||
.maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
|
||||
.maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
|
||||
.maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
|
||||
.maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
|
||||
.maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
|
||||
|
||||
.maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
|
||||
.maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
|
||||
};
|
||||
|
||||
static struct pci_device_id rtl92ee_pci_ids[] = {
|
||||
{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x818B, rtl92ee_hal_cfg)},
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(pci, rtl92ee_pci_ids);
|
||||
|
||||
MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
|
||||
MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("Realtek 8192EE 802.11n PCI wireless");
|
||||
MODULE_FIRMWARE("rtlwifi/rtl8192eefw.bin");
|
||||
|
||||
module_param_named(swenc, rtl92ee_mod_params.sw_crypto, bool, 0444);
|
||||
module_param_named(debug, rtl92ee_mod_params.debug, int, 0444);
|
||||
module_param_named(ips, rtl92ee_mod_params.inactiveps, bool, 0444);
|
||||
module_param_named(swlps, rtl92ee_mod_params.swctrl_lps, bool, 0444);
|
||||
module_param_named(fwlps, rtl92ee_mod_params.fwctrl_lps, bool, 0444);
|
||||
module_param_named(msi, rtl92ee_mod_params.msi_support, bool, 0444);
|
||||
module_param_named(disable_watchdog, rtl92ee_mod_params.disable_watchdog,
|
||||
bool, 0444);
|
||||
MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
|
||||
MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
|
||||
MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
|
||||
MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
|
||||
MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
|
||||
MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
|
||||
MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
|
||||
|
||||
static struct pci_driver rtl92ee_driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.id_table = rtl92ee_pci_ids,
|
||||
.probe = rtl_pci_probe,
|
||||
.remove = rtl_pci_disconnect,
|
||||
.driver.pm = &rtlwifi_pm_ops,
|
||||
};
|
||||
|
||||
module_pci_driver(rtl92ee_driver);
|
||||
33
drivers/net/wireless/rtlwifi/rtl8192ee/sw.h
Normal file
33
drivers/net/wireless/rtlwifi/rtl8192ee/sw.h
Normal file
@ -0,0 +1,33 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL92E_SW_H__
|
||||
#define __RTL92E_SW_H__
|
||||
|
||||
int rtl92ee_init_sw_vars(struct ieee80211_hw *hw);
|
||||
void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw);
|
||||
bool rtl92ee_get_btc_status(void);
|
||||
|
||||
#endif
|
||||
882
drivers/net/wireless/rtlwifi/rtl8192ee/table.c
Normal file
882
drivers/net/wireless/rtlwifi/rtl8192ee/table.c
Normal file
@ -0,0 +1,882 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Created on 2010/ 5/18, 1:41
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "table.h"
|
||||
u32 RTL8192EE_PHY_REG_ARRAY[] = {
|
||||
0x800, 0x80040000,
|
||||
0x804, 0x00000003,
|
||||
0x808, 0x0000FC00,
|
||||
0x80C, 0x0000000A,
|
||||
0x810, 0x10001331,
|
||||
0x814, 0x020C3D10,
|
||||
0x818, 0x02220385,
|
||||
0x81C, 0x00000000,
|
||||
0x820, 0x01000100,
|
||||
0x824, 0x00390204,
|
||||
0x828, 0x01000100,
|
||||
0x82C, 0x00390204,
|
||||
0x830, 0x32323232,
|
||||
0x834, 0x30303030,
|
||||
0x838, 0x30303030,
|
||||
0x83C, 0x30303030,
|
||||
0x840, 0x00010000,
|
||||
0x844, 0x00010000,
|
||||
0x848, 0x28282828,
|
||||
0x84C, 0x28282828,
|
||||
0x850, 0x00000000,
|
||||
0x854, 0x00000000,
|
||||
0x858, 0x009A009A,
|
||||
0x85C, 0x01000014,
|
||||
0x860, 0x66F60000,
|
||||
0x864, 0x061F0000,
|
||||
0x868, 0x30303030,
|
||||
0x86C, 0x30303030,
|
||||
0x870, 0x00000000,
|
||||
0x874, 0x55004200,
|
||||
0x878, 0x08080808,
|
||||
0x87C, 0x00000000,
|
||||
0x880, 0xB0000C1C,
|
||||
0x884, 0x00000001,
|
||||
0x888, 0x00000000,
|
||||
0x88C, 0xCC0000C0,
|
||||
0x890, 0x00000800,
|
||||
0x894, 0xFFFFFFFE,
|
||||
0x898, 0x40302010,
|
||||
0x900, 0x00000000,
|
||||
0x904, 0x00000023,
|
||||
0x908, 0x00000000,
|
||||
0x90C, 0x81121313,
|
||||
0x910, 0x806C0001,
|
||||
0x914, 0x00000001,
|
||||
0x918, 0x00000000,
|
||||
0x91C, 0x00010000,
|
||||
0x924, 0x00000001,
|
||||
0x928, 0x00000000,
|
||||
0x92C, 0x00000000,
|
||||
0x930, 0x00000000,
|
||||
0x934, 0x00000000,
|
||||
0x938, 0x00000000,
|
||||
0x93C, 0x00000000,
|
||||
0x940, 0x00000000,
|
||||
0x944, 0x00000000,
|
||||
0x94C, 0x00000008,
|
||||
0xA00, 0x00D0C7C8,
|
||||
0xA04, 0x81FF000C,
|
||||
0xA08, 0x8C838300,
|
||||
0xA0C, 0x2E68120F,
|
||||
0xA10, 0x95009B78,
|
||||
0xA14, 0x1114D028,
|
||||
0xA18, 0x00881117,
|
||||
0xA1C, 0x89140F00,
|
||||
0xA20, 0x1A1B0000,
|
||||
0xA24, 0x090E1317,
|
||||
0xA28, 0x00000204,
|
||||
0xA2C, 0x00D30000,
|
||||
0xA70, 0x101FBF00,
|
||||
0xA74, 0x00000007,
|
||||
0xA78, 0x00000900,
|
||||
0xA7C, 0x225B0606,
|
||||
0xA80, 0x218075B1,
|
||||
0xB38, 0x00000000,
|
||||
0xC00, 0x48071D40,
|
||||
0xC04, 0x03A05633,
|
||||
0xC08, 0x000000E4,
|
||||
0xC0C, 0x6C6C6C6C,
|
||||
0xC10, 0x08800000,
|
||||
0xC14, 0x40000100,
|
||||
0xC18, 0x08800000,
|
||||
0xC1C, 0x40000100,
|
||||
0xC20, 0x00000000,
|
||||
0xC24, 0x00000000,
|
||||
0xC28, 0x00000000,
|
||||
0xC2C, 0x00000000,
|
||||
0xC30, 0x69E9AC47,
|
||||
0xC34, 0x469652AF,
|
||||
0xC38, 0x49795994,
|
||||
0xC3C, 0x0A97971C,
|
||||
0xC40, 0x1F7C403F,
|
||||
0xC44, 0x000100B7,
|
||||
0xC48, 0xEC020107,
|
||||
0xC4C, 0x007F037F,
|
||||
0xFF010718, 0xABCD,
|
||||
0xC50, 0x00340220,
|
||||
0xCDCDCDCD, 0xCDCD,
|
||||
0xC50, 0x00340020,
|
||||
0xFF010718, 0xDEAD,
|
||||
0xC54, 0x0080801F,
|
||||
0xFF010718, 0xABCD,
|
||||
0xC58, 0x00000220,
|
||||
0xCDCDCDCD, 0xCDCD,
|
||||
0xC58, 0x00000020,
|
||||
0xFF010718, 0xDEAD,
|
||||
0xC5C, 0x00248492,
|
||||
0xC60, 0x00000000,
|
||||
0xC64, 0x7112848B,
|
||||
0xC68, 0x47C00BFF,
|
||||
0xC6C, 0x00000036,
|
||||
0xC70, 0x00000600,
|
||||
0xC74, 0x02013169,
|
||||
0xC78, 0x0000001F,
|
||||
0xC7C, 0x00B91612,
|
||||
0xFF010718, 0xABCD,
|
||||
0xC80, 0x2D4000B5,
|
||||
0xCDCDCDCD, 0xCDCD,
|
||||
0xC80, 0x40000100,
|
||||
0xFF010718, 0xDEAD,
|
||||
0xC84, 0x21F60000,
|
||||
0xFF010718, 0xABCD,
|
||||
0xC88, 0x2D4000B5,
|
||||
0xCDCDCDCD, 0xCDCD,
|
||||
0xC88, 0x40000100,
|
||||
0xFF010718, 0xDEAD,
|
||||
0xC8C, 0xA0E40000,
|
||||
0xC90, 0x00121820,
|
||||
0xC94, 0x00000000,
|
||||
0xC98, 0x00121820,
|
||||
0xC9C, 0x00007F7F,
|
||||
0xCA0, 0x00000000,
|
||||
0xCA4, 0x000300A0,
|
||||
0xCA8, 0x00000000,
|
||||
0xCAC, 0x00000000,
|
||||
0xCB0, 0x00000000,
|
||||
0xCB4, 0x00000000,
|
||||
0xCB8, 0x00000000,
|
||||
0xCBC, 0x28000000,
|
||||
0xCC0, 0x00000000,
|
||||
0xCC4, 0x00000000,
|
||||
0xCC8, 0x00000000,
|
||||
0xCCC, 0x00000000,
|
||||
0xCD0, 0x00000000,
|
||||
0xCD4, 0x00000000,
|
||||
0xCD8, 0x64B22427,
|
||||
0xCDC, 0x00766932,
|
||||
0xCE0, 0x00222222,
|
||||
0xCE4, 0x00040000,
|
||||
0xCE8, 0x77644302,
|
||||
0xCEC, 0x2F97D40C,
|
||||
0xD00, 0x00080740,
|
||||
0xD04, 0x00020403,
|
||||
0xD08, 0x0000907F,
|
||||
0xD0C, 0x20010201,
|
||||
0xD10, 0xA0633333,
|
||||
0xD14, 0x3333BC43,
|
||||
0xD18, 0x7A8F5B6B,
|
||||
0xD1C, 0x0000007F,
|
||||
0xD2C, 0xCC979975,
|
||||
0xD30, 0x00000000,
|
||||
0xD34, 0x80608000,
|
||||
0xD38, 0x00000000,
|
||||
0xD3C, 0x00127353,
|
||||
0xD40, 0x00000000,
|
||||
0xD44, 0x00000000,
|
||||
0xD48, 0x00000000,
|
||||
0xD4C, 0x00000000,
|
||||
0xD50, 0x6437140A,
|
||||
0xD54, 0x00000000,
|
||||
0xD58, 0x00000282,
|
||||
0xD5C, 0x30032064,
|
||||
0xD60, 0x4653DE68,
|
||||
0xD64, 0x04518A3C,
|
||||
0xD68, 0x00002101,
|
||||
0xD6C, 0x2A201C16,
|
||||
0xD70, 0x1812362E,
|
||||
0xD74, 0x322C2220,
|
||||
0xD78, 0x000E3C24,
|
||||
0xD80, 0x01081008,
|
||||
0xD84, 0x00000800,
|
||||
0xD88, 0xF0B50000,
|
||||
0xE00, 0x30303030,
|
||||
0xE04, 0x30303030,
|
||||
0xE08, 0x03903030,
|
||||
0xE10, 0x30303030,
|
||||
0xE14, 0x30303030,
|
||||
0xE18, 0x30303030,
|
||||
0xE1C, 0x30303030,
|
||||
0xE28, 0x00000000,
|
||||
0xE30, 0x1000DC1F,
|
||||
0xE34, 0x10008C1F,
|
||||
0xE38, 0x02140102,
|
||||
0xE3C, 0x681604C2,
|
||||
0xE40, 0x01007C00,
|
||||
0xE44, 0x01004800,
|
||||
0xE48, 0xFB000000,
|
||||
0xE4C, 0x000028D1,
|
||||
0xE50, 0x1000DC1F,
|
||||
0xE54, 0x10008C1F,
|
||||
0xE58, 0x02140102,
|
||||
0xE5C, 0x28160D05,
|
||||
0xE60, 0x00000008,
|
||||
0xE68, 0x0FC05656,
|
||||
0xE6C, 0x03C09696,
|
||||
0xE70, 0x03C09696,
|
||||
0xE74, 0x0C005656,
|
||||
0xE78, 0x0C005656,
|
||||
0xE7C, 0x0C005656,
|
||||
0xE80, 0x0C005656,
|
||||
0xE84, 0x03C09696,
|
||||
0xE88, 0x0C005656,
|
||||
0xE8C, 0x03C09696,
|
||||
0xED0, 0x03C09696,
|
||||
0xED4, 0x03C09696,
|
||||
0xED8, 0x03C09696,
|
||||
0xEDC, 0x0000D6D6,
|
||||
0xEE0, 0x0000D6D6,
|
||||
0xEEC, 0x0FC01616,
|
||||
0xEE4, 0xB0000C1C,
|
||||
0xEE8, 0x00000001,
|
||||
0xF14, 0x00000003,
|
||||
0xF4C, 0x00000000,
|
||||
0xF00, 0x00000300,
|
||||
};
|
||||
|
||||
u32 RTL8192EE_PHY_REG_ARRAY_PG[] = {
|
||||
0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200,
|
||||
0, 0, 1, 0x00000e08, 0x0000ff00, 0x00003200,
|
||||
0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200,
|
||||
0, 0, 1, 0x0000086c, 0xffffff00, 0x32323200,
|
||||
0, 0, 0, 0x00000e00, 0xffffffff, 0x34343636,
|
||||
0, 0, 1, 0x00000e00, 0xffffffff, 0x34343636,
|
||||
0, 0, 0, 0x00000e04, 0xffffffff, 0x28283032,
|
||||
0, 0, 1, 0x00000e04, 0xffffffff, 0x28283032,
|
||||
0, 0, 0, 0x00000e10, 0xffffffff, 0x34363840,
|
||||
0, 0, 1, 0x00000e10, 0xffffffff, 0x34363840,
|
||||
0, 0, 0, 0x00000e14, 0xffffffff, 0x26283032,
|
||||
0, 0, 1, 0x00000e14, 0xffffffff, 0x26283032,
|
||||
0, 0, 1, 0x00000e18, 0xffffffff, 0x36384040,
|
||||
0, 0, 1, 0x00000e1c, 0xffffffff, 0x24262832,
|
||||
0, 1, 0, 0x00000838, 0xffffff00, 0x32323200,
|
||||
0, 1, 1, 0x00000838, 0xffffff00, 0x32323200,
|
||||
0, 1, 0, 0x0000086c, 0x000000ff, 0x00000032,
|
||||
0, 1, 1, 0x0000086c, 0x000000ff, 0x00000032,
|
||||
0, 1, 0, 0x00000830, 0xffffffff, 0x34343636,
|
||||
0, 1, 1, 0x00000830, 0xffffffff, 0x34343636,
|
||||
0, 1, 0, 0x00000834, 0xffffffff, 0x28283032,
|
||||
0, 1, 1, 0x00000834, 0xffffffff, 0x28283032,
|
||||
0, 1, 0, 0x0000083c, 0xffffffff, 0x34363840,
|
||||
0, 1, 1, 0x0000083c, 0xffffffff, 0x34363840,
|
||||
0, 1, 0, 0x00000848, 0xffffffff, 0x26283032,
|
||||
0, 1, 1, 0x00000848, 0xffffffff, 0x26283032,
|
||||
0, 1, 1, 0x0000084c, 0xffffffff, 0x36384040,
|
||||
0, 1, 1, 0x00000868, 0xffffffff, 0x24262832
|
||||
};
|
||||
|
||||
u32 RTL8192EE_RADIOA_ARRAY[] = {
|
||||
0x07F, 0x00000082,
|
||||
0x081, 0x0003FC00,
|
||||
0x000, 0x00030000,
|
||||
0x008, 0x00008400,
|
||||
0x018, 0x00000407,
|
||||
0x019, 0x00000012,
|
||||
0x01B, 0x00000064,
|
||||
0x01E, 0x00080009,
|
||||
0x01F, 0x00000880,
|
||||
0x02F, 0x0001A060,
|
||||
0x03F, 0x00000000,
|
||||
0x042, 0x000060C0,
|
||||
0x057, 0x000D0000,
|
||||
0x058, 0x000BE180,
|
||||
0x067, 0x00001552,
|
||||
0x083, 0x00000000,
|
||||
0x0B0, 0x000FF9F1,
|
||||
0x0B1, 0x00055418,
|
||||
0x0B2, 0x0008CC00,
|
||||
0x0B4, 0x00043083,
|
||||
0x0B5, 0x00008166,
|
||||
0x0B6, 0x0000803E,
|
||||
0x0B7, 0x0001C69F,
|
||||
0x0B8, 0x0000407F,
|
||||
0x0B9, 0x00080001,
|
||||
0x0BA, 0x00040001,
|
||||
0x0BB, 0x00000400,
|
||||
0x0BF, 0x000C0000,
|
||||
0x0C2, 0x00002400,
|
||||
0x0C3, 0x00000009,
|
||||
0x0C4, 0x00040C91,
|
||||
0x0C5, 0x00099999,
|
||||
0x0C6, 0x000000A3,
|
||||
0x0C7, 0x00088820,
|
||||
0x0C8, 0x00076C06,
|
||||
0x0C9, 0x00000000,
|
||||
0x0CA, 0x00080000,
|
||||
0x0DF, 0x00000180,
|
||||
0x0EF, 0x000001A0,
|
||||
0x051, 0x00069545,
|
||||
0x052, 0x0007E45E,
|
||||
0x053, 0x00000071,
|
||||
0x056, 0x00051FF3,
|
||||
0x035, 0x000000A8,
|
||||
0x035, 0x000001E2,
|
||||
0x035, 0x000002A8,
|
||||
0x036, 0x00001C24,
|
||||
0x036, 0x00009C24,
|
||||
0x036, 0x00011C24,
|
||||
0x036, 0x00019C24,
|
||||
0x018, 0x00000C07,
|
||||
0x05A, 0x00048000,
|
||||
0x019, 0x000739D0,
|
||||
0xFF010718, 0xABCD,
|
||||
0x034, 0x0000A093,
|
||||
0x034, 0x0000908F,
|
||||
0x034, 0x0000808C,
|
||||
0x034, 0x0000704D,
|
||||
0x034, 0x0000604A,
|
||||
0x034, 0x00005047,
|
||||
0x034, 0x0000400A,
|
||||
0x034, 0x00003007,
|
||||
0x034, 0x00002004,
|
||||
0x034, 0x00001001,
|
||||
0x034, 0x00000000,
|
||||
0xCDCDCDCD, 0xCDCD,
|
||||
0x034, 0x0000ADD7,
|
||||
0x034, 0x00009DD4,
|
||||
0x034, 0x00008DD1,
|
||||
0x034, 0x00007DCE,
|
||||
0x034, 0x00006DCB,
|
||||
0x034, 0x00005DC8,
|
||||
0x034, 0x00004DC5,
|
||||
0x034, 0x000034CC,
|
||||
0x034, 0x0000244F,
|
||||
0x034, 0x0000144C,
|
||||
0x034, 0x00000014,
|
||||
0xFF010718, 0xDEAD,
|
||||
0x000, 0x00030159,
|
||||
0x084, 0x00068180,
|
||||
0x086, 0x0000014E,
|
||||
0x087, 0x00048E00,
|
||||
0x08E, 0x00065540,
|
||||
0x08F, 0x00088000,
|
||||
0x0EF, 0x000020A0,
|
||||
0xFF010718, 0xABCD,
|
||||
0x03B, 0x000F07B0,
|
||||
0xCDCDCDCD, 0xCDCD,
|
||||
0x03B, 0x000F02B0,
|
||||
0xFF010718, 0xDEAD,
|
||||
0x03B, 0x000EF7B0,
|
||||
0x03B, 0x000D4FB0,
|
||||
0x03B, 0x000CF060,
|
||||
0x03B, 0x000B0090,
|
||||
0x03B, 0x000A0080,
|
||||
0x03B, 0x00090080,
|
||||
0x03B, 0x0008F780,
|
||||
0xFF010718, 0xABCD,
|
||||
0x03B, 0x000787B0,
|
||||
0xCDCDCDCD, 0xCDCD,
|
||||
0x03B, 0x00078730,
|
||||
0xFF010718, 0xDEAD,
|
||||
0x03B, 0x00060FB0,
|
||||
0x03B, 0x0005FFA0,
|
||||
0x03B, 0x00040620,
|
||||
0x03B, 0x00037090,
|
||||
0x03B, 0x00020080,
|
||||
0x03B, 0x0001F060,
|
||||
0x03B, 0x0000FFB0,
|
||||
0x0EF, 0x000000A0,
|
||||
0x0FE, 0x00000000,
|
||||
0x018, 0x0000FC07,
|
||||
0x0FE, 0x00000000,
|
||||
0x0FE, 0x00000000,
|
||||
0x0FE, 0x00000000,
|
||||
0x0FE, 0x00000000,
|
||||
0x01E, 0x00000001,
|
||||
0x01F, 0x00080000,
|
||||
0x000, 0x00033E70,
|
||||
};
|
||||
|
||||
u32 RTL8192EE_RADIOB_ARRAY[] = {
|
||||
0x07F, 0x00000082,
|
||||
0x081, 0x0003FC00,
|
||||
0x000, 0x00030000,
|
||||
0x008, 0x00008400,
|
||||
0x018, 0x00000407,
|
||||
0x019, 0x00000012,
|
||||
0x01B, 0x00000064,
|
||||
0x01E, 0x00080009,
|
||||
0x01F, 0x00000880,
|
||||
0x02F, 0x0001A060,
|
||||
0x03F, 0x00000000,
|
||||
0x042, 0x000060C0,
|
||||
0x057, 0x000D0000,
|
||||
0x058, 0x000BE180,
|
||||
0x067, 0x00001552,
|
||||
0x07F, 0x00000082,
|
||||
0x081, 0x0003F000,
|
||||
0x083, 0x00000000,
|
||||
0x0DF, 0x00000180,
|
||||
0x0EF, 0x000001A0,
|
||||
0x051, 0x00069545,
|
||||
0x052, 0x0007E42E,
|
||||
0x053, 0x00000071,
|
||||
0x056, 0x00051FF3,
|
||||
0x035, 0x000000A8,
|
||||
0x035, 0x000001E0,
|
||||
0x035, 0x000002A8,
|
||||
0x036, 0x00001CA8,
|
||||
0x036, 0x00009C24,
|
||||
0x036, 0x00011C24,
|
||||
0x036, 0x00019C24,
|
||||
0x018, 0x00000C07,
|
||||
0x05A, 0x00048000,
|
||||
0x019, 0x000739D0,
|
||||
0xFF010718, 0xABCD,
|
||||
0x034, 0x0000A093,
|
||||
0x034, 0x0000908F,
|
||||
0x034, 0x0000808C,
|
||||
0x034, 0x0000704D,
|
||||
0x034, 0x0000604A,
|
||||
0x034, 0x00005047,
|
||||
0x034, 0x0000400A,
|
||||
0x034, 0x00003007,
|
||||
0x034, 0x00002004,
|
||||
0x034, 0x00001001,
|
||||
0x034, 0x00000000,
|
||||
0xCDCDCDCD, 0xCDCD,
|
||||
0x034, 0x0000ADD7,
|
||||
0x034, 0x00009DD4,
|
||||
0x034, 0x00008DD1,
|
||||
0x034, 0x00007DCE,
|
||||
0x034, 0x00006DCB,
|
||||
0x034, 0x00005DC8,
|
||||
0x034, 0x00004DC5,
|
||||
0x034, 0x000034CC,
|
||||
0x034, 0x0000244F,
|
||||
0x034, 0x0000144C,
|
||||
0x034, 0x00000014,
|
||||
0xFF010718, 0xDEAD,
|
||||
0x000, 0x00030159,
|
||||
0x084, 0x00068180,
|
||||
0x086, 0x000000CE,
|
||||
0x087, 0x00048A00,
|
||||
0x08E, 0x00065540,
|
||||
0x08F, 0x00088000,
|
||||
0x0EF, 0x000020A0,
|
||||
0xFF010718, 0xABCD,
|
||||
0x03B, 0x000F07B0,
|
||||
0xCDCDCDCD, 0xCDCD,
|
||||
0x03B, 0x000F02B0,
|
||||
0xFF010718, 0xDEAD,
|
||||
0x03B, 0x000EF7B0,
|
||||
0x03B, 0x000D4FB0,
|
||||
0x03B, 0x000CF060,
|
||||
0x03B, 0x000B0090,
|
||||
0x03B, 0x000A0080,
|
||||
0x03B, 0x00090080,
|
||||
0x03B, 0x0008F780,
|
||||
0xFF010718, 0xABCD,
|
||||
0x03B, 0x000787B0,
|
||||
0xCDCDCDCD, 0xCDCD,
|
||||
0x03B, 0x00078730,
|
||||
0xFF010718, 0xDEAD,
|
||||
0x03B, 0x00060FB0,
|
||||
0x03B, 0x0005FFA0,
|
||||
0x03B, 0x00040620,
|
||||
0x03B, 0x00037090,
|
||||
0x03B, 0x00020080,
|
||||
0x03B, 0x0001F060,
|
||||
0x03B, 0x0000FFB0,
|
||||
0x0EF, 0x000000A0,
|
||||
0x000, 0x00010159,
|
||||
0x0FE, 0x00000000,
|
||||
0x0FE, 0x00000000,
|
||||
0x0FE, 0x00000000,
|
||||
0x0FE, 0x00000000,
|
||||
0x01E, 0x00000001,
|
||||
0x01F, 0x00080000,
|
||||
0x000, 0x00033E70,
|
||||
};
|
||||
|
||||
u32 RTL8192EE_MAC_ARRAY[] = {
|
||||
0x011, 0x000000EB,
|
||||
0x012, 0x00000007,
|
||||
0x014, 0x00000075,
|
||||
0x303, 0x000000A7,
|
||||
0x428, 0x0000000A,
|
||||
0x429, 0x00000010,
|
||||
0x430, 0x00000000,
|
||||
0x431, 0x00000000,
|
||||
0x432, 0x00000000,
|
||||
0x433, 0x00000001,
|
||||
0x434, 0x00000004,
|
||||
0x435, 0x00000005,
|
||||
0x436, 0x00000007,
|
||||
0x437, 0x00000008,
|
||||
0x43C, 0x00000004,
|
||||
0x43D, 0x00000005,
|
||||
0x43E, 0x00000007,
|
||||
0x43F, 0x00000008,
|
||||
0x440, 0x0000005D,
|
||||
0x441, 0x00000001,
|
||||
0x442, 0x00000000,
|
||||
0x444, 0x00000010,
|
||||
0x445, 0x00000000,
|
||||
0x446, 0x00000000,
|
||||
0x447, 0x00000000,
|
||||
0x448, 0x00000000,
|
||||
0x449, 0x000000F0,
|
||||
0x44A, 0x0000000F,
|
||||
0x44B, 0x0000003E,
|
||||
0x44C, 0x00000010,
|
||||
0x44D, 0x00000000,
|
||||
0x44E, 0x00000000,
|
||||
0x44F, 0x00000000,
|
||||
0x450, 0x00000000,
|
||||
0x451, 0x000000F0,
|
||||
0x452, 0x0000000F,
|
||||
0x453, 0x00000000,
|
||||
0x456, 0x0000005E,
|
||||
0x460, 0x00000066,
|
||||
0x461, 0x00000066,
|
||||
0x4C8, 0x000000FF,
|
||||
0x4C9, 0x00000008,
|
||||
0x4CC, 0x000000FF,
|
||||
0x4CD, 0x000000FF,
|
||||
0x4CE, 0x00000001,
|
||||
0x500, 0x00000026,
|
||||
0x501, 0x000000A2,
|
||||
0x502, 0x0000002F,
|
||||
0x503, 0x00000000,
|
||||
0x504, 0x00000028,
|
||||
0x505, 0x000000A3,
|
||||
0x506, 0x0000005E,
|
||||
0x507, 0x00000000,
|
||||
0x508, 0x0000002B,
|
||||
0x509, 0x000000A4,
|
||||
0x50A, 0x0000005E,
|
||||
0x50B, 0x00000000,
|
||||
0x50C, 0x0000004F,
|
||||
0x50D, 0x000000A4,
|
||||
0x50E, 0x00000000,
|
||||
0x50F, 0x00000000,
|
||||
0x512, 0x0000001C,
|
||||
0x514, 0x0000000A,
|
||||
0x516, 0x0000000A,
|
||||
0x525, 0x0000004F,
|
||||
0x540, 0x00000012,
|
||||
0x541, 0x00000064,
|
||||
0x550, 0x00000010,
|
||||
0x551, 0x00000010,
|
||||
0x559, 0x00000002,
|
||||
0x55C, 0x00000050,
|
||||
0x55D, 0x000000FF,
|
||||
0x605, 0x00000030,
|
||||
0x608, 0x0000000E,
|
||||
0x609, 0x0000002A,
|
||||
0x620, 0x000000FF,
|
||||
0x621, 0x000000FF,
|
||||
0x622, 0x000000FF,
|
||||
0x623, 0x000000FF,
|
||||
0x624, 0x000000FF,
|
||||
0x625, 0x000000FF,
|
||||
0x626, 0x000000FF,
|
||||
0x627, 0x000000FF,
|
||||
0x638, 0x00000050,
|
||||
0x63C, 0x0000000A,
|
||||
0x63D, 0x0000000A,
|
||||
0x63E, 0x0000000E,
|
||||
0x63F, 0x0000000E,
|
||||
0x640, 0x00000040,
|
||||
0x642, 0x00000040,
|
||||
0x643, 0x00000000,
|
||||
0x652, 0x000000C8,
|
||||
0x66E, 0x00000005,
|
||||
0x700, 0x00000021,
|
||||
0x701, 0x00000043,
|
||||
0x702, 0x00000065,
|
||||
0x703, 0x00000087,
|
||||
0x708, 0x00000021,
|
||||
0x709, 0x00000043,
|
||||
0x70A, 0x00000065,
|
||||
0x70B, 0x00000087,
|
||||
};
|
||||
|
||||
u32 RTL8192EE_AGC_TAB_ARRAY[] = {
|
||||
0xFF010718, 0xABCD,
|
||||
0xC78, 0xFA000001,
|
||||
0xC78, 0xF9010001,
|
||||
0xC78, 0xF8020001,
|
||||
0xC78, 0xF7030001,
|
||||
0xC78, 0xF6040001,
|
||||
0xC78, 0xF5050001,
|
||||
0xC78, 0xF4060001,
|
||||
0xC78, 0xF3070001,
|
||||
0xC78, 0xF2080001,
|
||||
0xC78, 0xF1090001,
|
||||
0xC78, 0xF00A0001,
|
||||
0xC78, 0xEF0B0001,
|
||||
0xC78, 0xEE0C0001,
|
||||
0xC78, 0xED0D0001,
|
||||
0xC78, 0xEC0E0001,
|
||||
0xC78, 0xEB0F0001,
|
||||
0xC78, 0xEA100001,
|
||||
0xC78, 0xE9110001,
|
||||
0xC78, 0xE8120001,
|
||||
0xC78, 0xE7130001,
|
||||
0xC78, 0xE6140001,
|
||||
0xC78, 0xE5150001,
|
||||
0xC78, 0xE4160001,
|
||||
0xC78, 0xE3170001,
|
||||
0xC78, 0xE2180001,
|
||||
0xC78, 0xE1190001,
|
||||
0xC78, 0x8A1A0001,
|
||||
0xC78, 0x891B0001,
|
||||
0xC78, 0x881C0001,
|
||||
0xC78, 0x871D0001,
|
||||
0xC78, 0x861E0001,
|
||||
0xC78, 0x851F0001,
|
||||
0xC78, 0x84200001,
|
||||
0xC78, 0x83210001,
|
||||
0xC78, 0x82220001,
|
||||
0xC78, 0x6A230001,
|
||||
0xC78, 0x69240001,
|
||||
0xC78, 0x68250001,
|
||||
0xC78, 0x67260001,
|
||||
0xC78, 0x66270001,
|
||||
0xC78, 0x65280001,
|
||||
0xC78, 0x64290001,
|
||||
0xC78, 0x632A0001,
|
||||
0xC78, 0x622B0001,
|
||||
0xC78, 0x612C0001,
|
||||
0xC78, 0x602D0001,
|
||||
0xC78, 0x472E0001,
|
||||
0xC78, 0x462F0001,
|
||||
0xC78, 0x45300001,
|
||||
0xC78, 0x44310001,
|
||||
0xC78, 0x43320001,
|
||||
0xC78, 0x42330001,
|
||||
0xC78, 0x41340001,
|
||||
0xC78, 0x40350001,
|
||||
0xC78, 0x40360001,
|
||||
0xC78, 0x40370001,
|
||||
0xC78, 0x40380001,
|
||||
0xC78, 0x40390001,
|
||||
0xC78, 0x403A0001,
|
||||
0xC78, 0x403B0001,
|
||||
0xC78, 0x403C0001,
|
||||
0xC78, 0x403D0001,
|
||||
0xC78, 0x403E0001,
|
||||
0xC78, 0x403F0001,
|
||||
0xCDCDCDCD, 0xCDCD,
|
||||
0xC78, 0xFB000001,
|
||||
0xC78, 0xFB010001,
|
||||
0xC78, 0xFB020001,
|
||||
0xC78, 0xFB030001,
|
||||
0xC78, 0xFB040001,
|
||||
0xC78, 0xFB050001,
|
||||
0xC78, 0xFA060001,
|
||||
0xC78, 0xF9070001,
|
||||
0xC78, 0xF8080001,
|
||||
0xC78, 0xF7090001,
|
||||
0xC78, 0xF60A0001,
|
||||
0xC78, 0xF50B0001,
|
||||
0xC78, 0xF40C0001,
|
||||
0xC78, 0xF30D0001,
|
||||
0xC78, 0xF20E0001,
|
||||
0xC78, 0xF10F0001,
|
||||
0xC78, 0xF0100001,
|
||||
0xC78, 0xEF110001,
|
||||
0xC78, 0xEE120001,
|
||||
0xC78, 0xED130001,
|
||||
0xC78, 0xEC140001,
|
||||
0xC78, 0xEB150001,
|
||||
0xC78, 0xEA160001,
|
||||
0xC78, 0xE9170001,
|
||||
0xC78, 0xE8180001,
|
||||
0xC78, 0xE7190001,
|
||||
0xC78, 0xC81A0001,
|
||||
0xC78, 0xC71B0001,
|
||||
0xC78, 0xC61C0001,
|
||||
0xC78, 0x071D0001,
|
||||
0xC78, 0x061E0001,
|
||||
0xC78, 0x051F0001,
|
||||
0xC78, 0x04200001,
|
||||
0xC78, 0x03210001,
|
||||
0xC78, 0xAA220001,
|
||||
0xC78, 0xA9230001,
|
||||
0xC78, 0xA8240001,
|
||||
0xC78, 0xA7250001,
|
||||
0xC78, 0xA6260001,
|
||||
0xC78, 0x85270001,
|
||||
0xC78, 0x84280001,
|
||||
0xC78, 0x83290001,
|
||||
0xC78, 0x252A0001,
|
||||
0xC78, 0x242B0001,
|
||||
0xC78, 0x232C0001,
|
||||
0xC78, 0x222D0001,
|
||||
0xC78, 0x672E0001,
|
||||
0xC78, 0x662F0001,
|
||||
0xC78, 0x65300001,
|
||||
0xC78, 0x64310001,
|
||||
0xC78, 0x63320001,
|
||||
0xC78, 0x62330001,
|
||||
0xC78, 0x61340001,
|
||||
0xC78, 0x45350001,
|
||||
0xC78, 0x44360001,
|
||||
0xC78, 0x43370001,
|
||||
0xC78, 0x42380001,
|
||||
0xC78, 0x41390001,
|
||||
0xC78, 0x403A0001,
|
||||
0xC78, 0x403B0001,
|
||||
0xC78, 0x403C0001,
|
||||
0xC78, 0x403D0001,
|
||||
0xC78, 0x403E0001,
|
||||
0xC78, 0x403F0001,
|
||||
0xFF010718, 0xDEAD,
|
||||
0xFF010718, 0xABCD,
|
||||
0xC78, 0xFA400001,
|
||||
0xC78, 0xF9410001,
|
||||
0xC78, 0xF8420001,
|
||||
0xC78, 0xF7430001,
|
||||
0xC78, 0xF6440001,
|
||||
0xC78, 0xF5450001,
|
||||
0xC78, 0xF4460001,
|
||||
0xC78, 0xF3470001,
|
||||
0xC78, 0xF2480001,
|
||||
0xC78, 0xF1490001,
|
||||
0xC78, 0xF04A0001,
|
||||
0xC78, 0xEF4B0001,
|
||||
0xC78, 0xEE4C0001,
|
||||
0xC78, 0xED4D0001,
|
||||
0xC78, 0xEC4E0001,
|
||||
0xC78, 0xEB4F0001,
|
||||
0xC78, 0xEA500001,
|
||||
0xC78, 0xE9510001,
|
||||
0xC78, 0xE8520001,
|
||||
0xC78, 0xE7530001,
|
||||
0xC78, 0xE6540001,
|
||||
0xC78, 0xE5550001,
|
||||
0xC78, 0xE4560001,
|
||||
0xC78, 0xE3570001,
|
||||
0xC78, 0xE2580001,
|
||||
0xC78, 0xE1590001,
|
||||
0xC78, 0x8A5A0001,
|
||||
0xC78, 0x895B0001,
|
||||
0xC78, 0x885C0001,
|
||||
0xC78, 0x875D0001,
|
||||
0xC78, 0x865E0001,
|
||||
0xC78, 0x855F0001,
|
||||
0xC78, 0x84600001,
|
||||
0xC78, 0x83610001,
|
||||
0xC78, 0x82620001,
|
||||
0xC78, 0x6A630001,
|
||||
0xC78, 0x69640001,
|
||||
0xC78, 0x68650001,
|
||||
0xC78, 0x67660001,
|
||||
0xC78, 0x66670001,
|
||||
0xC78, 0x65680001,
|
||||
0xC78, 0x64690001,
|
||||
0xC78, 0x636A0001,
|
||||
0xC78, 0x626B0001,
|
||||
0xC78, 0x616C0001,
|
||||
0xC78, 0x606D0001,
|
||||
0xC78, 0x476E0001,
|
||||
0xC78, 0x466F0001,
|
||||
0xC78, 0x45700001,
|
||||
0xC78, 0x44710001,
|
||||
0xC78, 0x43720001,
|
||||
0xC78, 0x42730001,
|
||||
0xC78, 0x41740001,
|
||||
0xC78, 0x40750001,
|
||||
0xC78, 0x40760001,
|
||||
0xC78, 0x40770001,
|
||||
0xC78, 0x40780001,
|
||||
0xC78, 0x40790001,
|
||||
0xC78, 0x407A0001,
|
||||
0xC78, 0x407B0001,
|
||||
0xC78, 0x407C0001,
|
||||
0xC78, 0x407D0001,
|
||||
0xC78, 0x407E0001,
|
||||
0xC78, 0x407F0001,
|
||||
0xC50, 0x00040222,
|
||||
0xC50, 0x00040220,
|
||||
0xCDCDCDCD, 0xCDCD,
|
||||
0xC78, 0xFB400001,
|
||||
0xC78, 0xFB410001,
|
||||
0xC78, 0xFB420001,
|
||||
0xC78, 0xFB430001,
|
||||
0xC78, 0xFB440001,
|
||||
0xC78, 0xFB450001,
|
||||
0xC78, 0xFA460001,
|
||||
0xC78, 0xF9470001,
|
||||
0xC78, 0xF8480001,
|
||||
0xC78, 0xF7490001,
|
||||
0xC78, 0xF64A0001,
|
||||
0xC78, 0xF54B0001,
|
||||
0xC78, 0xF44C0001,
|
||||
0xC78, 0xF34D0001,
|
||||
0xC78, 0xF24E0001,
|
||||
0xC78, 0xF14F0001,
|
||||
0xC78, 0xF0500001,
|
||||
0xC78, 0xEF510001,
|
||||
0xC78, 0xEE520001,
|
||||
0xC78, 0xED530001,
|
||||
0xC78, 0xEC540001,
|
||||
0xC78, 0xEB550001,
|
||||
0xC78, 0xEA560001,
|
||||
0xC78, 0xE9570001,
|
||||
0xC78, 0xE8580001,
|
||||
0xC78, 0xE7590001,
|
||||
0xC78, 0xE65A0001,
|
||||
0xC78, 0xE55B0001,
|
||||
0xC78, 0xE45C0001,
|
||||
0xC78, 0xE35D0001,
|
||||
0xC78, 0xE25E0001,
|
||||
0xC78, 0xE15F0001,
|
||||
0xC78, 0x8A600001,
|
||||
0xC78, 0x89610001,
|
||||
0xC78, 0x88620001,
|
||||
0xC78, 0x87630001,
|
||||
0xC78, 0x86640001,
|
||||
0xC78, 0x85650001,
|
||||
0xC78, 0x84660001,
|
||||
0xC78, 0x83670001,
|
||||
0xC78, 0x82680001,
|
||||
0xC78, 0x6B690001,
|
||||
0xC78, 0x6A6A0001,
|
||||
0xC78, 0x696B0001,
|
||||
0xC78, 0x686C0001,
|
||||
0xC78, 0x676D0001,
|
||||
0xC78, 0x666E0001,
|
||||
0xC78, 0x656F0001,
|
||||
0xC78, 0x64700001,
|
||||
0xC78, 0x63710001,
|
||||
0xC78, 0x62720001,
|
||||
0xC78, 0x61730001,
|
||||
0xC78, 0x49740001,
|
||||
0xC78, 0x48750001,
|
||||
0xC78, 0x47760001,
|
||||
0xC78, 0x46770001,
|
||||
0xC78, 0x45780001,
|
||||
0xC78, 0x44790001,
|
||||
0xC78, 0x437A0001,
|
||||
0xC78, 0x427B0001,
|
||||
0xC78, 0x417C0001,
|
||||
0xC78, 0x407D0001,
|
||||
0xC78, 0x407E0001,
|
||||
0xC78, 0x407F0001,
|
||||
0xC50, 0x00040022,
|
||||
0xC50, 0x00040020,
|
||||
0xFF010718, 0xDEAD,
|
||||
};
|
||||
45
drivers/net/wireless/rtlwifi/rtl8192ee/table.h
Normal file
45
drivers/net/wireless/rtlwifi/rtl8192ee/table.h
Normal file
@ -0,0 +1,45 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Created on 2010/ 5/18, 1:41
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL92E_TABLE__H_
|
||||
#define __RTL92E_TABLE__H_
|
||||
|
||||
#include <linux/types.h>
|
||||
#define RTL8192EE_PHY_REG_ARRAY_LEN 448
|
||||
extern u32 RTL8192EE_PHY_REG_ARRAY[];
|
||||
#define RTL8192EE_PHY_REG_ARRAY_PG_LEN 168
|
||||
extern u32 RTL8192EE_PHY_REG_ARRAY_PG[];
|
||||
#define RTL8192EE_RADIOA_ARRAY_LEN 238
|
||||
extern u32 RTL8192EE_RADIOA_ARRAY[];
|
||||
#define RTL8192EE_RADIOB_ARRAY_LEN 198
|
||||
extern u32 RTL8192EE_RADIOB_ARRAY[];
|
||||
#define RTL8192EE_MAC_ARRAY_LEN 202
|
||||
extern u32 RTL8192EE_MAC_ARRAY[];
|
||||
#define RTL8192EE_AGC_TAB_ARRAY_LEN 532
|
||||
extern u32 RTL8192EE_AGC_TAB_ARRAY[];
|
||||
|
||||
#endif
|
||||
1300
drivers/net/wireless/rtlwifi/rtl8192ee/trx.c
Normal file
1300
drivers/net/wireless/rtlwifi/rtl8192ee/trx.c
Normal file
File diff suppressed because it is too large
Load Diff
860
drivers/net/wireless/rtlwifi/rtl8192ee/trx.h
Normal file
860
drivers/net/wireless/rtlwifi/rtl8192ee/trx.h
Normal file
@ -0,0 +1,860 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2014 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __RTL92E_TRX_H__
|
||||
#define __RTL92E_TRX_H__
|
||||
|
||||
#if (DMA_IS_64BIT == 1)
|
||||
#if (RTL8192EE_SEG_NUM == 2)
|
||||
#define TX_BD_DESC_SIZE 128
|
||||
#elif (RTL8192EE_SEG_NUM == 1)
|
||||
#define TX_BD_DESC_SIZE 64
|
||||
#elif (RTL8192EE_SEG_NUM == 0)
|
||||
#define TX_BD_DESC_SIZE 32
|
||||
#endif
|
||||
#else
|
||||
#if (RTL8192EE_SEG_NUM == 2)
|
||||
#define TX_BD_DESC_SIZE 64
|
||||
#elif (RTL8192EE_SEG_NUM == 1)
|
||||
#define TX_BD_DESC_SIZE 32
|
||||
#elif (RTL8192EE_SEG_NUM == 0)
|
||||
#define TX_BD_DESC_SIZE 16
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define TX_DESC_SIZE 64
|
||||
|
||||
#define RX_DRV_INFO_SIZE_UNIT 8
|
||||
|
||||
#define TX_DESC_NEXT_DESC_OFFSET 40
|
||||
#define USB_HWDESC_HEADER_LEN 40
|
||||
|
||||
#define RX_DESC_SIZE 24
|
||||
#define MAX_RECEIVE_BUFFER_SIZE 8192
|
||||
|
||||
#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val)
|
||||
#define SET_TX_DESC_OFFSET(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val)
|
||||
#define SET_TX_DESC_BMC(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val)
|
||||
#define SET_TX_DESC_HTC(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val)
|
||||
#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val)
|
||||
#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val)
|
||||
#define SET_TX_DESC_LINIP(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val)
|
||||
#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val)
|
||||
#define SET_TX_DESC_GF(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
|
||||
#define SET_TX_DESC_OWN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
|
||||
|
||||
#define GET_TX_DESC_PKT_SIZE(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 0, 16)
|
||||
#define GET_TX_DESC_OFFSET(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 16, 8)
|
||||
#define GET_TX_DESC_BMC(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 24, 1)
|
||||
#define GET_TX_DESC_HTC(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 25, 1)
|
||||
#define GET_TX_DESC_LAST_SEG(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 26, 1)
|
||||
#define GET_TX_DESC_FIRST_SEG(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 27, 1)
|
||||
#define GET_TX_DESC_LINIP(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 28, 1)
|
||||
#define GET_TX_DESC_NO_ACM(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 29, 1)
|
||||
#define GET_TX_DESC_GF(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 30, 1)
|
||||
#define GET_TX_DESC_OWN(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 31, 1)
|
||||
|
||||
#define SET_TX_DESC_MACID(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 7, __val)
|
||||
#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val)
|
||||
#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val)
|
||||
#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val)
|
||||
#define SET_TX_DESC_PIFS(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val)
|
||||
#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 5, __val)
|
||||
#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val)
|
||||
#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 22, 2, __val)
|
||||
#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 5, __val)
|
||||
#define SET_TX_DESC_MORE_DATA(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 29, 1, __val)
|
||||
#define SET_TX_DESC_TXOP_PS_CAP(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 30, 1, __val)
|
||||
#define SET_TX_DESC_TXOP_PS_MODE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 31, 1, __val)
|
||||
|
||||
#define GET_TX_DESC_MACID(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 0, 5)
|
||||
#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 5, 1)
|
||||
#define GET_TX_DESC_AGG_BREAK(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 6, 1)
|
||||
#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 7, 1)
|
||||
#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 8, 5)
|
||||
#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
|
||||
#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
|
||||
#define GET_TX_DESC_PIFS(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
|
||||
#define GET_TX_DESC_RATE_ID(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
|
||||
#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
|
||||
#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
|
||||
#define GET_TX_DESC_SEC_TYPE(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 22, 2)
|
||||
#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 24, 5)
|
||||
|
||||
#define SET_TX_DESC_PAID(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 9, __val)
|
||||
#define SET_TX_DESC_CCA_RTS(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 10, 2, __val)
|
||||
#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 12, 1, __val)
|
||||
#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 13, 1, __val)
|
||||
#define SET_TX_DESC_NULL_0(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 1, __val)
|
||||
#define SET_TX_DESC_NULL_1(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 15, 1, __val)
|
||||
#define SET_TX_DESC_BK(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 16, 1, __val)
|
||||
#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val)
|
||||
#define SET_TX_DESC_RAW(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val)
|
||||
#define SET_TX_DESC_SPE_RPT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 19, 1, __val)
|
||||
#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val)
|
||||
#define SET_TX_DESC_BT_NULL(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 23, 1, __val)
|
||||
#define SET_TX_DESC_GID(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 24, 6, __val)
|
||||
|
||||
#define SET_TX_DESC_WHEADER_LEN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 4, __val)
|
||||
#define SET_TX_DESC_CHK_EN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 4, 1, __val)
|
||||
#define SET_TX_DESC_EARLY_RATE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 5, 1, __val)
|
||||
#define SET_TX_DESC_HWSEQ_SEL(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 6, 2, __val)
|
||||
#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 1, __val)
|
||||
#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 9, 1, __val)
|
||||
#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 10, 1, __val)
|
||||
#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 11, 1, __val)
|
||||
#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 12, 1, __val)
|
||||
#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 13, 1, __val)
|
||||
#define SET_TX_DESC_HW_PORT_ID(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 14, 1, __val)
|
||||
#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 15, 1, __val)
|
||||
#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 1, __val)
|
||||
#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 17, 5, __val)
|
||||
#define SET_TX_DESC_NDPA(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 22, 2, __val)
|
||||
#define SET_TX_DESC_AMPDU_MAX_TIME(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 24, 8, __val)
|
||||
|
||||
/* Dword 4 */
|
||||
#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 7, __val)
|
||||
#define SET_TX_DESC_TRY_RATE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 7, 1, __val)
|
||||
#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 8, 5, __val)
|
||||
#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 13, 4, __val)
|
||||
#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 17, 1, __val)
|
||||
#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 18, 6, __val)
|
||||
#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 24, 5, __val)
|
||||
#define SET_TX_DESC_PCTS_ENABLE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 29, 1, __val)
|
||||
#define SET_TX_DESC_PCTS_MASK_IDX(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 30, 2, __val)
|
||||
|
||||
/* Dword 5 */
|
||||
#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 4, __val)
|
||||
#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 4, 1, __val)
|
||||
#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 5, 2, __val)
|
||||
#define SET_TX_DESC_DATA_LDPC(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 7, 1, __val)
|
||||
#define SET_TX_DESC_DATA_STBC(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 8, 2, __val)
|
||||
#define SET_TX_DESC_VCS_STBC(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 10, 2, __val)
|
||||
#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 12, 1, __val)
|
||||
#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 13, 4, __val)
|
||||
#define SET_TX_DESC_TX_ANT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 4, __val)
|
||||
#define SET_TX_DESC_TX_POWER_0_PSET(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 28, 3, __val)
|
||||
|
||||
/* Dword 6 */
|
||||
#define SET_TX_DESC_SW_DEFINE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 12, __val)
|
||||
#define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+24, 16, 3, __val)
|
||||
#define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+24, 19, 3, __val)
|
||||
#define SET_TX_DESC_ANTSEL_C(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+24, 22, 3, __val)
|
||||
#define SET_TX_DESC_ANTSEL_D(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+24, 25, 3, __val)
|
||||
|
||||
/* Dword 7 */
|
||||
#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 16, __val)
|
||||
#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+28, 24, 8, __val)
|
||||
|
||||
/* Dword 8 */
|
||||
#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+32, 0, 6, __val)
|
||||
#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+32, 6, 2, __val)
|
||||
#define SET_TX_DESC_DATA_RC(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+32, 8, 6, __val)
|
||||
#define SET_TX_DESC_ENABLE_HW_SELECT(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+32, 15, 1, __val)
|
||||
#define SET_TX_DESC_NEXT_HEAD_PAGE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+32, 16, 8, __val)
|
||||
#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+32, 24, 8, __val)
|
||||
|
||||
/* Dword 9 */
|
||||
#define SET_TX_DESC_PADDING_LENGTH(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+36, 0, 11, __val)
|
||||
#define SET_TX_DESC_TXBF_PATH(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+36, 11, 1, __val)
|
||||
#define SET_TX_DESC_SEQ(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+36, 12, 12, __val)
|
||||
#define SET_TX_DESC_FINAL_DATA_RATE(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+36, 24, 8, __val)
|
||||
|
||||
/* Dword 10 */
|
||||
#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val)
|
||||
|
||||
/* Dword 11*/
|
||||
#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+48, 0, 32, __val)
|
||||
|
||||
#define SET_EARLYMODE_PKTNUM(__paddr, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr, 0, 4, __val)
|
||||
#define SET_EARLYMODE_LEN0(__paddr, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr, 4, 15, __val)
|
||||
#define SET_EARLYMODE_LEN1(__paddr, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr, 16, 2, __val)
|
||||
#define SET_EARLYMODE_LEN1_1(__paddr, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr, 19, 13, __val)
|
||||
#define SET_EARLYMODE_LEN1_2(__paddr, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr+4, 0, 2, __val)
|
||||
#define SET_EARLYMODE_LEN2(__paddr, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr+4, 2, 15, __val)
|
||||
#define SET_EARLYMODE_LEN2_1(__paddr, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr, 2, 4, __val)
|
||||
#define SET_EARLYMODE_LEN2_2(__paddr, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr+4, 0, 8, __val)
|
||||
#define SET_EARLYMODE_LEN3(__paddr, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr+4, 17, 15, __val)
|
||||
#define SET_EARLYMODE_LEN4(__paddr, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__paddr+4, 20, 12, __val)
|
||||
|
||||
/* TX/RX buffer descriptor */
|
||||
|
||||
#define SET_TX_EXTBUFF_DESC_LEN(__pdesc, __val, __set) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16), 0, 16, __val)
|
||||
#define SET_TX_EXTBUFF_DESC_ADDR_LOW(__pdesc, __val, __set)\
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16)+4, 0, 32, __val)
|
||||
#define SET_TX_EXTBUFF_DESC_ADDR_HIGH(__pdesc, __val, __set)\
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16)+8, 0, 32, __val)
|
||||
|
||||
/* for Txfilldescroptor92ee, fill the desc content. */
|
||||
#if (DMA_IS_64BIT == 1)
|
||||
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pdesc, __offset, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16), 0, 16, __val)
|
||||
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pdesc, __offset, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16), 31, 1, __val)
|
||||
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pdesc, __offset, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16)+4, 0, 32, __val)
|
||||
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pdesc, __offset, __val)\
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16)+8, 0, 32, __val)
|
||||
#define GET_TXBUFFER_DESC_ADDR_LOW(__pdesc, __offset) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+(__offset*16)+4, 0, 32)
|
||||
#else
|
||||
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pdesc, __offset, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8), 0, 16, __val)
|
||||
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pdesc, __offset, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8), 31, 1, __val)
|
||||
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pdesc, __offset, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8)+4, 0, 32, __val)
|
||||
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pdesc, __offset, __val)
|
||||
#define GET_TXBUFFER_DESC_ADDR_LOW(__pdesc, __offset) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+(__offset*8)+4, 0, 32)
|
||||
#endif
|
||||
|
||||
/* Dword 0 */
|
||||
#define SET_TX_BUFF_DESC_LEN_0(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
|
||||
#define SET_TX_BUFF_DESC_PSB(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 16, 15, __val)
|
||||
#define SET_TX_BUFF_DESC_OWN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
|
||||
|
||||
/* Dword 1 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_0(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 32, __val)
|
||||
#if (DMA_IS_64BIT == 1)
|
||||
/* Dword 2 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_0(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 32, __val)
|
||||
/* Dword 3 / RESERVED 0 */
|
||||
/* Dword 4 */
|
||||
#define SET_TX_BUFF_DESC_LEN_1(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 16, __val)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_1(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 31, 1, __val)
|
||||
/* Dword 5 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_1(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 32, __val)
|
||||
/* Dword 6 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_1(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
|
||||
/* Dword 7 / RESERVED 0 */
|
||||
/* Dword 8 */
|
||||
#define SET_TX_BUFF_DESC_LEN_2(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+32, 0, 16, __val)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_2(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+32, 31, 1, __val)
|
||||
/* Dword 9 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_2(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+36, 0, 32, __val)
|
||||
/* Dword 10 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_2(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val)
|
||||
/* Dword 11 / RESERVED 0 */
|
||||
/* Dword 12 */
|
||||
#define SET_TX_BUFF_DESC_LEN_3(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+48, 0, 16, __val)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_3(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+48, 31, 1, __val)
|
||||
/* Dword 13 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_3(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+52, 0, 32, __val)
|
||||
/* Dword 14 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_3(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+56, 0, 32, __val)
|
||||
/* Dword 15 / RESERVED 0 */
|
||||
#else
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_0(__pdesc, __val)
|
||||
/* Dword 2 */
|
||||
#define SET_TX_BUFF_DESC_LEN_1(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 16, __val)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_1(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+8, 31, 1, __val)
|
||||
/* Dword 3 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_1(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 32, __val)
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_1(__pdesc, __val)
|
||||
/* Dword 4 */
|
||||
#define SET_TX_BUFF_DESC_LEN_2(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 16, __val)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_2(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+16, 31, 1, __val)
|
||||
/* Dword 5 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_2(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 32, __val)
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_2(__pdesc, __val)
|
||||
/* Dword 6 */
|
||||
#define SET_TX_BUFF_DESC_LEN_3(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 16, __val)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_3(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+24, 31, 1, __val)
|
||||
/* Dword 7 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_3(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_3(__pdesc, __val)
|
||||
#endif
|
||||
|
||||
/* RX buffer */
|
||||
|
||||
/* DWORD 0 */
|
||||
#define SET_RX_BUFFER_DESC_DATA_LENGTH(__status, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__status, 0, 14, __val)
|
||||
#define SET_RX_BUFFER_DESC_LS(__status, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__status, 15, 1, __val)
|
||||
#define SET_RX_BUFFER_DESC_FS(__status, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__status, 16, 1, __val)
|
||||
#define SET_RX_BUFFER_DESC_TOTAL_LENGTH(__status, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__status, 16, 15, __val)
|
||||
|
||||
#define GET_RX_BUFFER_DESC_OWN(__status) \
|
||||
LE_BITS_TO_4BYTE(__status, 31, 1)
|
||||
#define GET_RX_BUFFER_DESC_LS(__status) \
|
||||
LE_BITS_TO_4BYTE(__status, 15, 1)
|
||||
#define GET_RX_BUFFER_DESC_FS(__status) \
|
||||
LE_BITS_TO_4BYTE(__status, 16, 1)
|
||||
#define GET_RX_BUFFER_DESC_TOTAL_LENGTH(__status) \
|
||||
LE_BITS_TO_4BYTE(__status, 16, 15)
|
||||
|
||||
/* DWORD 1 */
|
||||
#define SET_RX_BUFFER_PHYSICAL_LOW(__status, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__status+4, 0, 32, __val)
|
||||
|
||||
/* DWORD 2 */
|
||||
#define SET_RX_BUFFER_PHYSICAL_HIGH(__status, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__status+8, 0, 32, __val)
|
||||
|
||||
#define GET_RX_DESC_PKT_LEN(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 0, 14)
|
||||
#define GET_RX_DESC_CRC32(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 14, 1)
|
||||
#define GET_RX_DESC_ICV(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 15, 1)
|
||||
#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 16, 4)
|
||||
#define GET_RX_DESC_SECURITY(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 20, 3)
|
||||
#define GET_RX_DESC_QOS(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 23, 1)
|
||||
#define GET_RX_DESC_SHIFT(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 24, 2)
|
||||
#define GET_RX_DESC_PHYST(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 26, 1)
|
||||
#define GET_RX_DESC_SWDEC(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 27, 1)
|
||||
#define GET_RX_DESC_LS(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 28, 1)
|
||||
#define GET_RX_DESC_FS(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 29, 1)
|
||||
#define GET_RX_DESC_EOR(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 30, 1)
|
||||
#define GET_RX_DESC_OWN(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc, 31, 1)
|
||||
|
||||
#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
|
||||
#define SET_RX_DESC_EOR(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
|
||||
#define SET_RX_DESC_OWN(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
|
||||
|
||||
#define GET_RX_DESC_MACID(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 0, 7)
|
||||
#define GET_RX_DESC_TID(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 8, 4)
|
||||
#define GET_RX_DESC_MACID_VLD(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 12, 1)
|
||||
#define GET_RX_DESC_AMSDU(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
|
||||
#define GET_RX_DESC_RXID_MATCH(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
|
||||
#define GET_RX_DESC_PAGGR(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
|
||||
#define GET_RX_DESC_A1_FIT(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
|
||||
#define GET_RX_DESC_TCPOFFLOAD_CHKERR(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
|
||||
#define GET_RX_DESC_TCPOFFLOAD_IPVER(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
|
||||
#define GET_RX_DESC_TCPOFFLOAD_IS_TCPUDP(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 22, 1)
|
||||
#define GET_RX_DESC_TCPOFFLOAD_CHK_VLD(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 23, 1)
|
||||
#define GET_RX_DESC_PAM(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 24, 1)
|
||||
#define GET_RX_DESC_PWR(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 25, 1)
|
||||
#define GET_RX_DESC_MD(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 26, 1)
|
||||
#define GET_RX_DESC_MF(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 27, 1)
|
||||
#define GET_RX_DESC_TYPE(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 28, 2)
|
||||
#define GET_RX_DESC_MC(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 30, 1)
|
||||
#define GET_RX_DESC_BC(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+4, 31, 1)
|
||||
#define GET_RX_DESC_SEQ(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+8, 0, 12)
|
||||
#define GET_RX_DESC_FRAG(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+8, 12, 4)
|
||||
#define GET_RX_DESC_RX_IS_QOS(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+8, 16, 1)
|
||||
|
||||
#define GET_RX_DESC_RXMCS(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 0, 7)
|
||||
#define GET_RX_DESC_HTC(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 10, 1)
|
||||
#define GET_RX_STATUS_DESC_EOSP(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 11, 1)
|
||||
#define GET_RX_STATUS_DESC_BSSID_FIT(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 12, 2)
|
||||
#define GET_RX_STATUS_DESC_DMA_AGG_NUM(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 16, 8)
|
||||
#define GET_RX_STATUS_DESC_PATTERN_MATCH(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 29, 1)
|
||||
#define GET_RX_STATUS_DESC_UNICAST_MATCH(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_MAGIC_MATCH(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+12, 31, 1)
|
||||
|
||||
#define GET_RX_DESC_TSFL(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+20, 0, 32)
|
||||
|
||||
#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+24, 0, 32)
|
||||
#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
|
||||
LE_BITS_TO_4BYTE(__pdesc+28, 0, 32)
|
||||
|
||||
#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
|
||||
#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
|
||||
SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
|
||||
|
||||
/* TX report 2 format in Rx desc*/
|
||||
|
||||
#define GET_RX_RPT2_DESC_PKT_LEN(__status) \
|
||||
LE_BITS_TO_4BYTE(__status, 0, 9)
|
||||
#define GET_RX_RPT2_DESC_MACID_VALID_1(__status) \
|
||||
LE_BITS_TO_4BYTE(__status+16, 0, 32)
|
||||
#define GET_RX_RPT2_DESC_MACID_VALID_2(__status) \
|
||||
LE_BITS_TO_4BYTE(__status+20, 0, 32)
|
||||
|
||||
#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
|
||||
do { \
|
||||
if (_size > TX_DESC_NEXT_DESC_OFFSET) \
|
||||
memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
|
||||
else \
|
||||
memset(__pdesc, 0, _size); \
|
||||
} while (0)
|
||||
|
||||
#define RTL92EE_RX_HAL_IS_CCK_RATE(rxmcs)\
|
||||
(rxmcs == DESC92C_RATE1M ||\
|
||||
rxmcs == DESC92C_RATE2M ||\
|
||||
rxmcs == DESC92C_RATE5_5M ||\
|
||||
rxmcs == DESC92C_RATE11M)
|
||||
|
||||
#define IS_LITTLE_ENDIAN 1
|
||||
|
||||
struct phy_rx_agc_info_t {
|
||||
#if IS_LITTLE_ENDIAN
|
||||
u8 gain:7, trsw:1;
|
||||
#else
|
||||
u8 trsw:1, gain:7;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct phy_status_rpt {
|
||||
struct phy_rx_agc_info_t path_agc[2];
|
||||
u8 ch_corr[2];
|
||||
u8 cck_sig_qual_ofdm_pwdb_all;
|
||||
u8 cck_agc_rpt_ofdm_cfosho_a;
|
||||
u8 cck_rpt_b_ofdm_cfosho_b;
|
||||
u8 rsvd_1;
|
||||
u8 noise_power_db_msb;
|
||||
u8 path_cfotail[2];
|
||||
u8 pcts_mask[2];
|
||||
u8 stream_rxevm[2];
|
||||
u8 path_rxsnr[2];
|
||||
u8 noise_power_db_lsb;
|
||||
u8 rsvd_2[3];
|
||||
u8 stream_csi[2];
|
||||
u8 stream_target_csi[2];
|
||||
u8 sig_evm;
|
||||
u8 rsvd_3;
|
||||
#if IS_LITTLE_ENDIAN
|
||||
u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/
|
||||
u8 sgi_en:1;
|
||||
u8 rxsc:2;
|
||||
u8 idle_long:1;
|
||||
u8 r_ant_train_en:1;
|
||||
u8 ant_sel_b:1;
|
||||
u8 ant_sel:1;
|
||||
#else /* _BIG_ENDIAN_ */
|
||||
u8 ant_sel:1;
|
||||
u8 ant_sel_b:1;
|
||||
u8 r_ant_train_en:1;
|
||||
u8 idle_long:1;
|
||||
u8 rxsc:2;
|
||||
u8 sgi_en:1;
|
||||
u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/
|
||||
#endif
|
||||
} __packed;
|
||||
|
||||
struct rx_fwinfo {
|
||||
u8 gain_trsw[4];
|
||||
u8 pwdb_all;
|
||||
u8 cfosho[4];
|
||||
u8 cfotail[4];
|
||||
char rxevm[2];
|
||||
char rxsnr[4];
|
||||
u8 pdsnr[2];
|
||||
u8 csi_current[2];
|
||||
u8 csi_target[2];
|
||||
u8 sigevm;
|
||||
u8 max_ex_pwr;
|
||||
u8 ex_intf_flag:1;
|
||||
u8 sgi_en:1;
|
||||
u8 rxsc:2;
|
||||
u8 reserve:4;
|
||||
} __packed;
|
||||
|
||||
struct tx_desc {
|
||||
u32 pktsize:16;
|
||||
u32 offset:8;
|
||||
u32 bmc:1;
|
||||
u32 htc:1;
|
||||
u32 lastseg:1;
|
||||
u32 firstseg:1;
|
||||
u32 linip:1;
|
||||
u32 noacm:1;
|
||||
u32 gf:1;
|
||||
u32 own:1;
|
||||
|
||||
u32 macid:6;
|
||||
u32 rsvd0:2;
|
||||
u32 queuesel:5;
|
||||
u32 rd_nav_ext:1;
|
||||
u32 lsig_txop_en:1;
|
||||
u32 pifs:1;
|
||||
u32 rateid:4;
|
||||
u32 nav_usehdr:1;
|
||||
u32 en_descid:1;
|
||||
u32 sectype:2;
|
||||
u32 pktoffset:8;
|
||||
|
||||
u32 rts_rc:6;
|
||||
u32 data_rc:6;
|
||||
u32 agg_en:1;
|
||||
u32 rdg_en:1;
|
||||
u32 bar_retryht:2;
|
||||
u32 agg_break:1;
|
||||
u32 morefrag:1;
|
||||
u32 raw:1;
|
||||
u32 ccx:1;
|
||||
u32 ampdudensity:3;
|
||||
u32 bt_int:1;
|
||||
u32 ant_sela:1;
|
||||
u32 ant_selb:1;
|
||||
u32 txant_cck:2;
|
||||
u32 txant_l:2;
|
||||
u32 txant_ht:2;
|
||||
|
||||
u32 nextheadpage:8;
|
||||
u32 tailpage:8;
|
||||
u32 seq:12;
|
||||
u32 cpu_handle:1;
|
||||
u32 tag1:1;
|
||||
u32 trigger_int:1;
|
||||
u32 hwseq_en:1;
|
||||
|
||||
u32 rtsrate:5;
|
||||
u32 apdcfe:1;
|
||||
u32 qos:1;
|
||||
u32 hwseq_ssn:1;
|
||||
u32 userrate:1;
|
||||
u32 dis_rtsfb:1;
|
||||
u32 dis_datafb:1;
|
||||
u32 cts2self:1;
|
||||
u32 rts_en:1;
|
||||
u32 hwrts_en:1;
|
||||
u32 portid:1;
|
||||
u32 pwr_status:3;
|
||||
u32 waitdcts:1;
|
||||
u32 cts2ap_en:1;
|
||||
u32 txsc:2;
|
||||
u32 stbc:2;
|
||||
u32 txshort:1;
|
||||
u32 txbw:1;
|
||||
u32 rtsshort:1;
|
||||
u32 rtsbw:1;
|
||||
u32 rtssc:2;
|
||||
u32 rtsstbc:2;
|
||||
|
||||
u32 txrate:6;
|
||||
u32 shortgi:1;
|
||||
u32 ccxt:1;
|
||||
u32 txrate_fb_lmt:5;
|
||||
u32 rtsrate_fb_lmt:4;
|
||||
u32 retrylmt_en:1;
|
||||
u32 txretrylmt:6;
|
||||
u32 usb_txaggnum:8;
|
||||
|
||||
u32 txagca:5;
|
||||
u32 txagcb:5;
|
||||
u32 usemaxlen:1;
|
||||
u32 maxaggnum:5;
|
||||
u32 mcsg1maxlen:4;
|
||||
u32 mcsg2maxlen:4;
|
||||
u32 mcsg3maxlen:4;
|
||||
u32 mcs7sgimaxlen:4;
|
||||
|
||||
u32 txbuffersize:16;
|
||||
u32 sw_offset30:8;
|
||||
u32 sw_offset31:4;
|
||||
u32 rsvd1:1;
|
||||
u32 antsel_c:1;
|
||||
u32 null_0:1;
|
||||
u32 null_1:1;
|
||||
|
||||
u32 txbuffaddr;
|
||||
u32 txbufferaddr64;
|
||||
u32 nextdescaddress;
|
||||
u32 nextdescaddress64;
|
||||
|
||||
u32 reserve_pass_pcie_mm_limit[4];
|
||||
} __packed;
|
||||
|
||||
struct rx_desc {
|
||||
u32 length:14;
|
||||
u32 crc32:1;
|
||||
u32 icverror:1;
|
||||
u32 drv_infosize:4;
|
||||
u32 security:3;
|
||||
u32 qos:1;
|
||||
u32 shift:2;
|
||||
u32 phystatus:1;
|
||||
u32 swdec:1;
|
||||
u32 lastseg:1;
|
||||
u32 firstseg:1;
|
||||
u32 eor:1;
|
||||
u32 own:1;
|
||||
|
||||
u32 macid:6;
|
||||
u32 tid:4;
|
||||
u32 hwrsvd:5;
|
||||
u32 paggr:1;
|
||||
u32 faggr:1;
|
||||
u32 a1_fit:4;
|
||||
u32 a2_fit:4;
|
||||
u32 pam:1;
|
||||
u32 pwr:1;
|
||||
u32 moredata:1;
|
||||
u32 morefrag:1;
|
||||
u32 type:2;
|
||||
u32 mc:1;
|
||||
u32 bc:1;
|
||||
|
||||
u32 seq:12;
|
||||
u32 frag:4;
|
||||
u32 nextpktlen:14;
|
||||
u32 nextind:1;
|
||||
u32 rsvd:1;
|
||||
|
||||
u32 rxmcs:6;
|
||||
u32 rxht:1;
|
||||
u32 amsdu:1;
|
||||
u32 splcp:1;
|
||||
u32 bandwidth:1;
|
||||
u32 htc:1;
|
||||
u32 tcpchk_rpt:1;
|
||||
u32 ipcchk_rpt:1;
|
||||
u32 tcpchk_valid:1;
|
||||
u32 hwpcerr:1;
|
||||
u32 hwpcind:1;
|
||||
u32 iv0:16;
|
||||
|
||||
u32 iv1;
|
||||
|
||||
u32 tsfl;
|
||||
|
||||
u32 bufferaddress;
|
||||
u32 bufferaddress64;
|
||||
|
||||
} __packed;
|
||||
|
||||
void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
|
||||
u8 queue_index);
|
||||
u16 rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw,
|
||||
u8 queue_index);
|
||||
void rtl92ee_get_available_desc(struct ieee80211_hw *hw, u8 queue_index);
|
||||
void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
|
||||
u8 *tx_bd_desc, u8 *desc, u8 queue_index,
|
||||
struct sk_buff *skb, dma_addr_t addr);
|
||||
|
||||
void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw,
|
||||
struct ieee80211_hdr *hdr, u8 *pdesc_tx,
|
||||
u8 *pbd_desc_tx,
|
||||
struct ieee80211_tx_info *info,
|
||||
struct ieee80211_sta *sta,
|
||||
struct sk_buff *skb,
|
||||
u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
|
||||
bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw,
|
||||
struct rtl_stats *status,
|
||||
struct ieee80211_rx_status *rx_status,
|
||||
u8 *pdesc, struct sk_buff *skb);
|
||||
void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
|
||||
u8 desc_name, u8 *val);
|
||||
|
||||
u32 rtl92ee_get_desc(u8 *pdesc, bool istx, u8 desc_name);
|
||||
bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index);
|
||||
void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
|
||||
void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
|
||||
bool firstseg, bool lastseg,
|
||||
struct sk_buff *skb);
|
||||
u32 rtl92ee_rx_command_packet(struct ieee80211_hw *hw,
|
||||
struct rtl_stats status,
|
||||
struct sk_buff *skb);
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user