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Renesas display drivers changes for v5.1:

Browse Source 
- R8A774C0 support
 - D3/E3 RGB output routing fixes
 - Miscellaneous fixes
 - Constify drm_bridge .mode_set() arguments
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Merge tag 'du-next-20190114' of git://linuxtv.org/pinchartl/media into drm-next

Renesas display drivers changes for v5.1:

- R8A774C0 support
- D3/E3 RGB output routing fixes
- Miscellaneous fixes
- Constify drm_bridge .mode_set() arguments

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1743477.dgErSCK0Q8@avalon
This commit is contained in:
Dave Airlie 2019-01-17 08:48:42 +10:00
commit b122153c71
47 changed files with 347 additions and 306 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
View File

@ -8,6 +8,7 @@ Required properties:
- compatible : Shall contain one of
- "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
- "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders
- "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
- "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
- "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
@ -25,7 +26,7 @@ Required properties:
- clock-names: Name of the clocks. This property is model-dependent.
- The functional clock, which mandatory for all models, shall be listed
first, and shall be named "fck".
- On R8A77990 and R8A77995, the LVDS encoder can use the EXTAL or
- On R8A77990, R8A77995 and R8A774C0, the LVDS encoder can use the EXTAL or
DU_DOTCLKINx clocks. Those clocks are optional. When supplied they must be
named "extal" and "dclkin.x" respectively, with "x" being the DU_DOTCLKIN
numerical index.

2
Documentation/devicetree/bindings/display/renesas,du.txt
View File

@ -7,6 +7,7 @@ Required Properties:
- "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU
- "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
- "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU
- "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU
- "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
- "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
- "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
@ -57,6 +58,7 @@ corresponding to each DU output.
R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - -
R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 -
R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 -
R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - -

4
drivers/gpu/drm/bridge/adv7511/adv7511.h
View File

@ -395,7 +395,7 @@ static inline int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511)
#ifdef CONFIG_DRM_I2C_ADV7533
void adv7533_dsi_power_on(struct adv7511 *adv);
void adv7533_dsi_power_off(struct adv7511 *adv);
void adv7533_mode_set(struct adv7511 *adv, struct drm_display_mode *mode);
void adv7533_mode_set(struct adv7511 *adv, const struct drm_display_mode *mode);
int adv7533_patch_registers(struct adv7511 *adv);
int adv7533_patch_cec_registers(struct adv7511 *adv);
int adv7533_attach_dsi(struct adv7511 *adv);
@ -411,7 +411,7 @@ static inline void adv7533_dsi_power_off(struct adv7511 *adv)
}
static inline void adv7533_mode_set(struct adv7511 *adv,
struct drm_display_mode *mode)
const struct drm_display_mode *mode)
{
}

8
drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
View File

@ -676,8 +676,8 @@ static enum drm_mode_status adv7511_mode_valid(struct adv7511 *adv7511,
}
static void adv7511_mode_set(struct adv7511 *adv7511,
struct drm_display_mode *mode,
struct drm_display_mode *adj_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adj_mode)
{
unsigned int low_refresh_rate;
unsigned int hsync_polarity = 0;
@ -839,8 +839,8 @@ static void adv7511_bridge_disable(struct drm_bridge *bridge)
}
static void adv7511_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adj_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adj_mode)
{
struct adv7511 *adv = bridge_to_adv7511(bridge);

2
drivers/gpu/drm/bridge/adv7511/adv7533.c
View File

@ -108,7 +108,7 @@ void adv7533_dsi_power_off(struct adv7511 *adv)
regmap_write(adv->regmap_cec, 0x27, 0x0b);
}
void adv7533_mode_set(struct adv7511 *adv, struct drm_display_mode *mode)
void adv7533_mode_set(struct adv7511 *adv, const struct drm_display_mode *mode)
{
struct mipi_dsi_device *dsi = adv->dsi;
int lanes, ret;

4
drivers/gpu/drm/bridge/analogix-anx78xx.c
View File

@ -1082,8 +1082,8 @@ static void anx78xx_bridge_disable(struct drm_bridge *bridge)
}
static void anx78xx_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
struct hdmi_avi_infoframe frame;

4
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
View File

@ -1361,8 +1361,8 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
}
static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *orig_mode,
struct drm_display_mode *mode)
const struct drm_display_mode *orig_mode,
const struct drm_display_mode *mode)
{
struct analogix_dp_device *dp = bridge->driver_private;
struct drm_display_info *display_info = &dp->connector.display_info;

4
drivers/gpu/drm/bridge/sii902x.c
View File

@ -232,8 +232,8 @@ static void sii902x_bridge_enable(struct drm_bridge *bridge)
}
static void sii902x_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adj)
const struct drm_display_mode *mode,
const struct drm_display_mode *adj)
{
struct sii902x *sii902x = bridge_to_sii902x(bridge);
struct regmap *regmap = sii902x->regmap;

4
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
View File

@ -1998,8 +1998,8 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
}
static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *orig_mode,
struct drm_display_mode *mode)
const struct drm_display_mode *orig_mode,
const struct drm_display_mode *mode)
{
struct dw_hdmi *hdmi = bridge->driver_private;

18
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
View File

@ -248,7 +248,7 @@ static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi)
* The controller should generate 2 frames before
* preparing the peripheral.
*/
static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode)
static void dw_mipi_dsi_wait_for_two_frames(const struct drm_display_mode *mode)
{
int refresh, two_frames;
@ -564,7 +564,7 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
}
static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
struct drm_display_mode *mode)
const struct drm_display_mode *mode)
{
u32 val = 0, color = 0;
@ -607,7 +607,7 @@ static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
}
static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
struct drm_display_mode *mode)
const struct drm_display_mode *mode)
{
/*
* TODO dw drv improvements
@ -642,7 +642,7 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
/* Get lane byte clock cycles. */
static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
struct drm_display_mode *mode,
const struct drm_display_mode *mode,
u32 hcomponent)
{
u32 frac, lbcc;
@ -658,7 +658,7 @@ static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
}
static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
struct drm_display_mode *mode)
const struct drm_display_mode *mode)
{
u32 htotal, hsa, hbp, lbcc;
@ -681,7 +681,7 @@ static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
}
static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
struct drm_display_mode *mode)
const struct drm_display_mode *mode)
{
u32 vactive, vsa, vfp, vbp;
@ -818,7 +818,7 @@ static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi)
}
static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi,
struct drm_display_mode *adjusted_mode)
const struct drm_display_mode *adjusted_mode)
{
const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
void *priv_data = dsi->plat_data->priv_data;
@ -861,8 +861,8 @@ static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi,
}
static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);

9
drivers/gpu/drm/bridge/tc358767.c
View File

@ -203,7 +203,7 @@ struct tc_data {
/* display edid */
struct edid *edid;
/* current mode */
struct drm_display_mode *mode;
const struct drm_display_mode *mode;
u32 rev;
u8 assr;
@ -648,7 +648,8 @@ static int tc_get_display_props(struct tc_data *tc)
return ret;
}
static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
static int tc_set_video_mode(struct tc_data *tc,
const struct drm_display_mode *mode)
{
int ret;
int vid_sync_dly;
@ -1113,8 +1114,8 @@ static enum drm_mode_status tc_connector_mode_valid(struct drm_connector *connec
}
static void tc_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adj)
const struct drm_display_mode *mode,
const struct drm_display_mode *adj)
{
struct tc_data *tc = bridge_to_tc(bridge);

4
drivers/gpu/drm/drm_bridge.c
View File

@ -294,8 +294,8 @@ EXPORT_SYMBOL(drm_bridge_post_disable);
* Note: the bridge passed should be the one closest to the encoder
*/
void drm_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
if (!bridge)
return;

4
drivers/gpu/drm/exynos/exynos_drm_mic.c
View File

@ -246,8 +246,8 @@ static void mic_post_disable(struct drm_bridge *bridge)
}
static void mic_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
struct exynos_mic *mic = bridge->driver_private;

6
drivers/gpu/drm/i2c/tda998x_drv.c
View File

@ -845,7 +845,7 @@ static int tda998x_write_aif(struct tda998x_priv *priv,
}
static void
tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
tda998x_write_avi(struct tda998x_priv *priv, const struct drm_display_mode *mode)
{
union hdmi_infoframe frame;
@ -1339,8 +1339,8 @@ static void tda998x_bridge_disable(struct drm_bridge *bridge)
}
static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
unsigned long tmds_clock;

4
drivers/gpu/drm/mediatek/mtk_hdmi.c
View File

@ -1370,8 +1370,8 @@ static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge)
}
static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);

2
drivers/gpu/drm/msm/dsi/dsi.h
View File

@ -168,7 +168,7 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,
bool is_dual_dsi);
int msm_dsi_host_power_off(struct mipi_dsi_host *host);
int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
struct drm_display_mode *mode);
const struct drm_display_mode *mode);
struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
unsigned long *panel_flags);
struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host);

2
drivers/gpu/drm/msm/dsi/dsi_host.c
View File

@ -2424,7 +2424,7 @@ int msm_dsi_host_power_off(struct mipi_dsi_host *host)
}
int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
struct drm_display_mode *mode)
const struct drm_display_mode *mode)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);

4
drivers/gpu/drm/msm/dsi/dsi_manager.c
View File

@ -527,8 +527,8 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge *bridge)
}
static void dsi_mgr_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
int id = dsi_mgr_bridge_get_id(bridge);
struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);

4
drivers/gpu/drm/msm/edp/edp_bridge.c
View File

@ -52,8 +52,8 @@ static void edp_bridge_post_disable(struct drm_bridge *bridge)
}
static void edp_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
struct drm_device *dev = bridge->dev;
struct drm_connector *connector;

4
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
View File

@ -207,8 +207,8 @@ static void msm_hdmi_bridge_post_disable(struct drm_bridge *bridge)
}
static void msm_hdmi_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
struct hdmi *hdmi = hdmi_bridge->hdmi;

43
drivers/gpu/drm/rcar-du/rcar_du_crtc.c
View File

@ -11,7 +11,6 @@
#include <linux/mutex.h>
#include <linux/sys_soc.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
@ -22,6 +21,7 @@
#include "rcar_du_crtc.h"
#include "rcar_du_drv.h"
#include "rcar_du_encoder.h"
#include "rcar_du_kms.h"
#include "rcar_du_plane.h"
#include "rcar_du_regs.h"
@ -316,26 +316,6 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
}
void rcar_du_crtc_route_output(struct drm_crtc *crtc,
enum rcar_du_output output)
{
struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
struct rcar_du_device *rcdu = rcrtc->group->dev;
/*
* Store the route from the CRTC output to the DU output. The DU will be
* configured when starting the CRTC.
*/
rcrtc->outputs |= BIT(output);
/*
* Store RGB routing to DPAD0, the hardware will be configured when
* starting the CRTC.
*/
if (output == RCAR_DU_OUTPUT_DPAD0)
rcdu->dpad0_source = rcrtc->index;
}
static unsigned int plane_zpos(struct rcar_du_plane *plane)
{
return plane->plane.state->normalized_zpos;
@ -655,6 +635,24 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
* CRTC Functions
*/
static int rcar_du_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(state);
struct drm_encoder *encoder;
/* Store the routes from the CRTC output to the DU outputs. */
rstate->outputs = 0;
drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
rstate->outputs |= BIT(renc->output);
}
return 0;
}
static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,
struct drm_crtc_state *old_state)
{
@ -678,8 +676,6 @@ static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc,
crtc->state->event = NULL;
}
spin_unlock_irq(&crtc->dev->event_lock);
rcrtc->outputs = 0;
}
static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
@ -755,6 +751,7 @@ enum drm_mode_status rcar_du_crtc_mode_valid(struct drm_crtc *crtc,
}
static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
.atomic_check = rcar_du_crtc_atomic_check,
.atomic_begin = rcar_du_crtc_atomic_begin,
.atomic_flush = rcar_du_crtc_atomic_flush,
.atomic_enable = rcar_du_crtc_atomic_enable,

8
drivers/gpu/drm/rcar-du/rcar_du_crtc.h
View File

@ -14,7 +14,6 @@
#include <linux/spinlock.h>
#include <linux/wait.h>
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <media/vsp1.h>
@ -37,7 +36,6 @@ struct rcar_du_vsp;
* @vblank_lock: protects vblank_wait and vblank_count
* @vblank_wait: wait queue used to signal vertical blanking
* @vblank_count: number of vertical blanking interrupts to wait for
* @outputs: bitmask of the outputs (enum rcar_du_output) driven by this CRTC
* @group: CRTC group this CRTC belongs to
* @vsp: VSP feeding video to this CRTC
* @vsp_pipe: index of the VSP pipeline feeding video to this CRTC
@ -61,8 +59,6 @@ struct rcar_du_crtc {
wait_queue_head_t vblank_wait;
unsigned int vblank_count;
unsigned int outputs;
struct rcar_du_group *group;
struct rcar_du_vsp *vsp;
unsigned int vsp_pipe;
@ -77,11 +73,13 @@ struct rcar_du_crtc {
* struct rcar_du_crtc_state - Driver-specific CRTC state
* @state: base DRM CRTC state
* @crc: CRC computation configuration
* @outputs: bitmask of the outputs (enum rcar_du_output) driven by this CRTC
*/
struct rcar_du_crtc_state {
struct drm_crtc_state state;
struct vsp1_du_crc_config crc;
unsigned int outputs;
};
#define to_rcar_crtc_state(s) container_of(s, struct rcar_du_crtc_state, state)
@ -102,8 +100,6 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc);
void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc);
void rcar_du_crtc_route_output(struct drm_crtc *crtc,
enum rcar_du_output output);
void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc);
void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set);

42
drivers/gpu/drm/rcar-du/rcar_du_drv.c
View File

@ -17,7 +17,6 @@
#include <linux/slab.h>
#include <linux/wait.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_cma_helper.h>
@ -36,7 +35,6 @@
static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
.gen = 2,
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC,
.channels_mask = BIT(1) | BIT(0),
@ -59,7 +57,6 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
.gen = 2,
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC,
.channels_mask = BIT(1) | BIT(0),
@ -81,7 +78,6 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
.gen = 2,
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC,
.channels_mask = BIT(1) | BIT(0),
@ -105,8 +101,34 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
},
};
static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
.gen = 3,
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_VSP1_SOURCE,
.channels_mask = BIT(1) | BIT(0),
.routes = {
/*
* R8A774C0 has one RGB output and two LVDS outputs
*/
[RCAR_DU_OUTPUT_DPAD0] = {
.possible_crtcs = BIT(0) | BIT(1),
.port = 0,
},
[RCAR_DU_OUTPUT_LVDS0] = {
.possible_crtcs = BIT(0),
.port = 1,
},
[RCAR_DU_OUTPUT_LVDS1] = {
.possible_crtcs = BIT(1),
.port = 2,
},
},
.num_lvds = 2,
.lvds_clk_mask = BIT(1) | BIT(0),
};
static const struct rcar_du_device_info rcar_du_r8a7779_info = {
.gen = 2,
.gen = 1,
.features = RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC,
.channels_mask = BIT(1) | BIT(0),
@ -129,7 +151,6 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
static const struct rcar_du_device_info rcar_du_r8a7790_info = {
.gen = 2,
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC,
.quirks = RCAR_DU_QUIRK_ALIGN_128B,
@ -159,7 +180,6 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
static const struct rcar_du_device_info rcar_du_r8a7791_info = {
.gen = 2,
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC,
.channels_mask = BIT(1) | BIT(0),
@ -183,7 +203,6 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
static const struct rcar_du_device_info rcar_du_r8a7792_info = {
.gen = 2,
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC,
.channels_mask = BIT(1) | BIT(0),
@ -203,7 +222,6 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
static const struct rcar_du_device_info rcar_du_r8a7794_info = {
.gen = 2,
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC,
.channels_mask = BIT(1) | BIT(0),
@ -226,7 +244,6 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
static const struct rcar_du_device_info rcar_du_r8a7795_info = {
.gen = 3,
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS
| RCAR_DU_FEATURE_VSP1_SOURCE
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC,
@ -260,7 +277,6 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
static const struct rcar_du_device_info rcar_du_r8a7796_info = {
.gen = 3,
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS
| RCAR_DU_FEATURE_VSP1_SOURCE
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC,
@ -290,7 +306,6 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
static const struct rcar_du_device_info rcar_du_r8a77965_info = {
.gen = 3,
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS
| RCAR_DU_FEATURE_VSP1_SOURCE
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC,
@ -320,7 +335,6 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
static const struct rcar_du_device_info rcar_du_r8a77970_info = {
.gen = 3,
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS
| RCAR_DU_FEATURE_VSP1_SOURCE
| RCAR_DU_FEATURE_INTERLACED
| RCAR_DU_FEATURE_TVM_SYNC,
@ -342,7 +356,6 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
.gen = 3,
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS
| RCAR_DU_FEATURE_VSP1_SOURCE,
.channels_mask = BIT(1) | BIT(0),
.routes = {
@ -372,6 +385,7 @@ static const struct of_device_id rcar_du_of_table[] = {
{ .compatible = "renesas,du-r8a7744", .data = &rzg1_du_r8a7743_info },
{ .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info },
{ .compatible = "renesas,du-r8a77470", .data = &rzg1_du_r8a77470_info },
{ .compatible = "renesas,du-r8a774c0", .data = &rcar_du_r8a774c0_info },
{ .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info },
{ .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info },
{ .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },

9
drivers/gpu/drm/rcar-du/rcar_du_drv.h
View File

@ -20,13 +20,13 @@
struct clk;
struct device;
struct drm_device;
struct drm_property;
struct rcar_du_device;
#define RCAR_DU_FEATURE_CRTC_IRQ_CLOCK BIT(0) /* Per-CRTC IRQ and clock */
#define RCAR_DU_FEATURE_EXT_CTRL_REGS BIT(1) /* Has extended control registers */
#define RCAR_DU_FEATURE_VSP1_SOURCE BIT(2) /* Has inputs from VSP1 */
#define RCAR_DU_FEATURE_INTERLACED BIT(3) /* HW supports interlaced */
#define RCAR_DU_FEATURE_TVM_SYNC BIT(4) /* Has TV switch/sync modes */
#define RCAR_DU_FEATURE_VSP1_SOURCE BIT(1) /* Has inputs from VSP1 */
#define RCAR_DU_FEATURE_INTERLACED BIT(2) /* HW supports interlaced */
#define RCAR_DU_FEATURE_TVM_SYNC BIT(3) /* Has TV switch/sync modes */
#define RCAR_DU_QUIRK_ALIGN_128B BIT(0) /* Align pitches to 128 bytes */
@ -89,6 +89,7 @@ struct rcar_du_device {
} props;
unsigned int dpad0_source;
unsigned int dpad1_source;
unsigned int vspd1_sink;
};

11
drivers/gpu/drm/rcar-du/rcar_du_encoder.c
View File

@ -9,7 +9,6 @@
#include <linux/export.h>
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_panel.h>
@ -22,17 +21,7 @@
* Encoder
*/
static void rcar_du_encoder_mode_set(struct drm_encoder *encoder,
struct drm_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
rcar_du_crtc_route_output(crtc_state->crtc, renc->output);
}
static const struct drm_encoder_helper_funcs encoder_helper_funcs = {
.atomic_mode_set = rcar_du_encoder_mode_set,
};
static const struct drm_encoder_funcs encoder_funcs = {

2
drivers/gpu/drm/rcar-du/rcar_du_encoder.h
View File

@ -10,10 +10,8 @@
#ifndef __RCAR_DU_ENCODER_H__
#define __RCAR_DU_ENCODER_H__
#include <drm/drm_crtc.h>
#include <drm/drm_encoder.h>
struct drm_panel;
struct rcar_du_device;
struct rcar_du_encoder {

51
drivers/gpu/drm/rcar-du/rcar_du_group.c
View File

@ -147,7 +147,7 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp)
rcar_du_group_setup_pins(rgrp);
if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) {
if (rcdu->info->gen >= 2) {
rcar_du_group_setup_defr8(rgrp);
rcar_du_group_setup_didsr(rgrp);
}
@ -262,7 +262,7 @@ int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
unsigned int index;
int ret;
if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
if (rcdu->info->gen < 2)
return 0;
/*
@ -287,9 +287,50 @@ int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
return 0;
}
static void rcar_du_group_set_dpad_levels(struct rcar_du_group *rgrp)
{
static const u32 doflr_values[2] = {
DOFLR_HSYCFL0 | DOFLR_VSYCFL0 | DOFLR_ODDFL0 |
DOFLR_DISPFL0 | DOFLR_CDEFL0 | DOFLR_RGBFL0,
DOFLR_HSYCFL1 | DOFLR_VSYCFL1 | DOFLR_ODDFL1 |
DOFLR_DISPFL1 | DOFLR_CDEFL1 | DOFLR_RGBFL1,
};
static const u32 dpad_mask = BIT(RCAR_DU_OUTPUT_DPAD1)
| BIT(RCAR_DU_OUTPUT_DPAD0);
struct rcar_du_device *rcdu = rgrp->dev;
u32 doflr = DOFLR_CODE;
unsigned int i;
if (rcdu->info->gen < 2)
return;
/*
* The DPAD outputs can't be controlled directly. However, the parallel
* output of the DU channels routed to DPAD can be set to fixed levels
* through the DOFLR group register. Use this to turn the DPAD on or off
* by driving fixed low-level signals at the output of any DU channel
* not routed to a DPAD output. This doesn't affect the DU output
* signals going to other outputs, such as the internal LVDS and HDMI
* encoders.
*/
for (i = 0; i < rgrp->num_crtcs; ++i) {
struct rcar_du_crtc_state *rstate;
struct rcar_du_crtc *rcrtc;
rcrtc = &rcdu->crtcs[rgrp->index * 2 + i];
rstate = to_rcar_crtc_state(rcrtc->crtc.state);
if (!(rstate->outputs & dpad_mask))
doflr |= doflr_values[i];
}
rcar_du_group_write(rgrp, DOFLR, doflr);
}
int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
{
struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
struct rcar_du_device *rcdu = rgrp->dev;
u32 dorcr = rcar_du_group_read(rgrp, DORCR);
dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
@ -299,12 +340,14 @@ int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
* CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
* by default.
*/
if (crtc0->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
if (rcdu->dpad1_source == rgrp->index * 2)
dorcr |= DORCR_PG2D_DS1;
else
dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;
rcar_du_group_write(rgrp, DORCR, dorcr);
rcar_du_group_set_dpad_levels(rgrp);
return rcar_du_set_dpad0_vsp1_routing(rgrp->dev);
}

23
drivers/gpu/drm/rcar-du/rcar_du_kms.c
View File

@ -7,7 +7,6 @@
* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
*/
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
@ -278,6 +277,28 @@ static int rcar_du_atomic_check(struct drm_device *dev,
static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
{
struct drm_device *dev = old_state->dev;
struct rcar_du_device *rcdu = dev->dev_private;
struct drm_crtc_state *crtc_state;
struct drm_crtc *crtc;
unsigned int i;
/*
* Store RGB routing to DPAD0 and DPAD1, the hardware will be configured
* when starting the CRTCs.
*/
rcdu->dpad1_source = -1;
for_each_new_crtc_in_state(old_state, crtc, crtc_state, i) {
struct rcar_du_crtc_state *rcrtc_state =
to_rcar_crtc_state(crtc_state);
struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD0))
rcdu->dpad0_source = rcrtc->index;
if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
rcdu->dpad1_source = rcrtc->index;
}
/* Apply the atomic update. */
drm_atomic_helper_commit_modeset_disables(dev, old_state);

93
drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7790.dts
View File

@ -7,70 +7,63 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target-path = "/";
__overlay__ {
#address-cells = <2>;
#size-cells = <2>;
lvds@feb90000 {
compatible = "renesas,r8a7790-lvds";
reg = <0 0xfeb90000 0 0x1c>;
&{/} {
#address-cells = <2>;
#size-cells = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
lvds@feb90000 {
compatible = "renesas,r8a7790-lvds";
reg = <0 0xfeb90000 0 0x1c>;
port@0 {
reg = <0>;
lvds0_input: endpoint {
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_input: endpoint {
};
};
lvds@feb94000 {
compatible = "renesas,r8a7790-lvds";
reg = <0 0xfeb94000 0 0x1c>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds1_input: endpoint {
};
};
port@1 {
reg = <1>;
lvds1_out: endpoint {
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
fragment@1 {
target-path = "/display@feb00000/ports";
__overlay__ {
port@1 {
endpoint {
remote-endpoint = <&lvds0_input>;
lvds@feb94000 {
compatible = "renesas,r8a7790-lvds";
reg = <0 0xfeb94000 0 0x1c>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds1_input: endpoint {
};
};
port@2 {
endpoint {
remote-endpoint = <&lvds1_input>;
port@1 {
reg = <1>;
lvds1_out: endpoint {
};
};
};
};
};
&{/display@feb00000/ports} {
port@1 {
endpoint {
remote-endpoint = <&lvds0_input>;
};
};
port@2 {
endpoint {
remote-endpoint = <&lvds1_input>;
};
};
};

53
drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7791.dts
View File

@ -7,44 +7,37 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target-path = "/";
__overlay__ {
#address-cells = <2>;
#size-cells = <2>;
lvds@feb90000 {
compatible = "renesas,r8a7791-lvds";
reg = <0 0xfeb90000 0 0x1c>;
&{/} {
#address-cells = <2>;
#size-cells = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
lvds@feb90000 {
compatible = "renesas,r8a7791-lvds";
reg = <0 0xfeb90000 0 0x1c>;
port@0 {
reg = <0>;
lvds0_input: endpoint {
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_input: endpoint {
};
};
};
};
fragment@1 {
target-path = "/display@feb00000/ports";
__overlay__ {
port@1 {
endpoint {
remote-endpoint = <&lvds0_input>;
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
};
&{/display@feb00000/ports} {
port@1 {
endpoint {
remote-endpoint = <&lvds0_input>;
};
};
};

53
drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7793.dts
View File

@ -7,44 +7,37 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target-path = "/";
__overlay__ {
#address-cells = <2>;
#size-cells = <2>;
lvds@feb90000 {
compatible = "renesas,r8a7793-lvds";
reg = <0 0xfeb90000 0 0x1c>;
&{/} {
#address-cells = <2>;
#size-cells = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
lvds@feb90000 {
compatible = "renesas,r8a7793-lvds";
reg = <0 0xfeb90000 0 0x1c>;
port@0 {
reg = <0>;
lvds0_input: endpoint {
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_input: endpoint {
};
};
};
};
fragment@1 {
target-path = "/display@feb00000/ports";
__overlay__ {
port@1 {
endpoint {
remote-endpoint = <&lvds0_input>;
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
};
&{/display@feb00000/ports} {
port@1 {
endpoint {
remote-endpoint = <&lvds0_input>;
};
};
};

55
drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7795.dts
View File

@ -7,44 +7,37 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target-path = "/soc";
__overlay__ {
#address-cells = <2>;
#size-cells = <2>;
lvds@feb90000 {
compatible = "renesas,r8a7795-lvds";
reg = <0 0xfeb90000 0 0x14>;
&{/soc} {
#address-cells = <2>;
#size-cells = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
lvds@feb90000 {
compatible = "renesas,r8a7795-lvds";
reg = <0 0xfeb90000 0 0x14>;
port@0 {
reg = <0>;
lvds0_input: endpoint {
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_input: endpoint {
};
};
};
};
fragment@1 {
target-path = "/soc/display@feb00000/ports";
__overlay__ {
port@3 {
endpoint {
remote-endpoint = <&lvds0_input>;
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
};
&{/soc/display@feb00000/ports} {
port@3 {
endpoint {
remote-endpoint = <&lvds0_input>;
};
};
};

55
drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7796.dts
View File

@ -7,44 +7,37 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target-path = "/soc";
__overlay__ {
#address-cells = <2>;
#size-cells = <2>;
lvds@feb90000 {
compatible = "renesas,r8a7796-lvds";
reg = <0 0xfeb90000 0 0x14>;
&{/soc} {
#address-cells = <2>;
#size-cells = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
lvds@feb90000 {
compatible = "renesas,r8a7796-lvds";
reg = <0 0xfeb90000 0 0x14>;
port@0 {
reg = <0>;
lvds0_input: endpoint {
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_input: endpoint {
};
};
};
};
fragment@1 {
target-path = "/soc/display@feb00000/ports";
__overlay__ {
port@3 {
endpoint {
remote-endpoint = <&lvds0_input>;
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
};
&{/soc/display@feb00000/ports} {
port@3 {
endpoint {
remote-endpoint = <&lvds0_input>;
};
};
};

1
drivers/gpu/drm/rcar-du/rcar_du_plane.c
View File

@ -7,7 +7,6 @@
* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
*/
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>

3
drivers/gpu/drm/rcar-du/rcar_du_plane.h
View File

@ -10,8 +10,7 @@
#ifndef __RCAR_DU_PLANE_H__
#define __RCAR_DU_PLANE_H__
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_plane.h>
struct rcar_du_format_info;
struct rcar_du_group;

1
drivers/gpu/drm/rcar-du/rcar_du_vsp.c
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@ -7,7 +7,6 @@
* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
*/
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>

3
drivers/gpu/drm/rcar-du/rcar_du_vsp.h
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@ -10,8 +10,7 @@
#ifndef __RCAR_DU_VSP_H__
#define __RCAR_DU_VSP_H__
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_plane.h>
struct rcar_du_format_info;
struct rcar_du_vsp;

15
drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c
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@ -35,6 +35,20 @@ static const struct rcar_hdmi_phy_params rcar_hdmi_phy_params[] = {
{ ~0UL, 0x0000, 0x0000, 0x0000 },
};
static enum drm_mode_status
rcar_hdmi_mode_valid(struct drm_connector *connector,
const struct drm_display_mode *mode)
{
/*
* The maximum supported clock frequency is 297 MHz, as shown in the PHY
* parameters table.
*/
if (mode->clock > 297000)
return MODE_CLOCK_HIGH;
return MODE_OK;
}
static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi,
const struct dw_hdmi_plat_data *pdata,
unsigned long mpixelclock)
@ -59,6 +73,7 @@ static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi,
}
static const struct dw_hdmi_plat_data rcar_dw_hdmi_plat_data = {
.mode_valid = rcar_hdmi_mode_valid,
.configure_phy = rcar_hdmi_phy_configure,
};

5
drivers/gpu/drm/rcar-du/rcar_lvds.c
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@ -520,8 +520,8 @@ static void rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds)
}
static void rcar_lvds_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
@ -785,6 +785,7 @@ static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
static const struct of_device_id rcar_lvds_of_table[] = {
{ .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
{ .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info },
{ .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info },
{ .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
{ .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },

2
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
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@ -467,7 +467,7 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
}
static int
dw_mipi_dsi_get_lane_mbps(void *priv_data, struct drm_display_mode *mode,
dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
unsigned long mode_flags, u32 lanes, u32 format,
unsigned int *lane_mbps)
{

4
drivers/gpu/drm/shmobile/shmob_drm_drv.c
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@ -229,8 +229,8 @@ static int shmob_drm_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
sdev->mmio = devm_ioremap_resource(&pdev->dev, res);
if (sdev->mmio == NULL)
return -ENOMEM;
if (IS_ERR(sdev->mmio))
return PTR_ERR(sdev->mmio);
ret = shmob_drm_setup_clocks(sdev, pdata->clk_source);
if (ret < 0)

4
drivers/gpu/drm/sti/sti_dvo.c
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@ -277,8 +277,8 @@ static void sti_dvo_pre_enable(struct drm_bridge *bridge)
}
static void sti_dvo_set_mode(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
struct sti_dvo *dvo = bridge->driver_private;
struct sti_mixer *mixer = to_sti_mixer(dvo->encoder->crtc);

4
drivers/gpu/drm/sti/sti_hda.c
View File

@ -508,8 +508,8 @@ static void sti_hda_pre_enable(struct drm_bridge *bridge)
}
static void sti_hda_set_mode(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
struct sti_hda *hda = bridge->driver_private;
u32 mode_idx;

4
drivers/gpu/drm/sti/sti_hdmi.c
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@ -917,8 +917,8 @@ static void sti_hdmi_pre_enable(struct drm_bridge *bridge)
}
static void sti_hdmi_set_mode(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
struct sti_hdmi *hdmi = bridge->driver_private;
int ret;

2
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
View File

@ -215,7 +215,7 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
}
static int
dw_mipi_dsi_get_lane_mbps(void *priv_data, struct drm_display_mode *mode,
dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
unsigned long mode_flags, u32 lanes, u32 format,
unsigned int *lane_mbps)
{

3
include/drm/bridge/dw_mipi_dsi.h
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@ -14,7 +14,8 @@ struct dw_mipi_dsi;
struct dw_mipi_dsi_phy_ops {
int (*init)(void *priv_data);
int (*get_lane_mbps)(void *priv_data, struct drm_display_mode *mode,
int (*get_lane_mbps)(void *priv_data,
const struct drm_display_mode *mode,
unsigned long mode_flags, u32 lanes, u32 format,
unsigned int *lane_mbps);
};

8
include/drm/drm_bridge.h
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@ -196,8 +196,8 @@ struct drm_bridge_funcs {
* the DRM framework will have to be extended with DRM bridge states.
*/
void (*mode_set)(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode);
/**
* @pre_enable:
*
@ -310,8 +310,8 @@ enum drm_mode_status drm_bridge_mode_valid(struct drm_bridge *bridge,
void drm_bridge_disable(struct drm_bridge *bridge);
void drm_bridge_post_disable(struct drm_bridge *bridge);
void drm_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode);
void drm_bridge_pre_enable(struct drm_bridge *bridge);
void drm_bridge_enable(struct drm_bridge *bridge);