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drm/i915: extract intel_set_pipe_timings from crtc_mode_set
Version 2: call intel_set_pipe_timings from both i9xx_crtc_mode_set and ironlake_crtc_mode_set, instead of just ironlake, as requested by Daniel Vetter. The problem caused by calling this function from i9xx_crtc_mode_set too is that now on i9xx we write to PIPESRC before writing to DSPSIZE and DSPPOS. I could not find any evidence in our documentation that this won't work, and the docs actually say the pipe registers should be set before the plane registers. Version 3: don't remove pipeconf bits on i9xx_crtc_mode_set. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -4290,6 +4290,55 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
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I915_WRITE(DPLL(pipe), dpll);
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}
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static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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enum pipe pipe = intel_crtc->pipe;
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uint32_t vsyncshift;
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if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
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/* the chip adds 2 halflines automatically */
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adjusted_mode->crtc_vtotal -= 1;
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adjusted_mode->crtc_vblank_end -= 1;
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vsyncshift = adjusted_mode->crtc_hsync_start
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- adjusted_mode->crtc_htotal / 2;
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} else {
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vsyncshift = 0;
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}
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if (INTEL_INFO(dev)->gen > 3)
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I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
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I915_WRITE(HTOTAL(pipe),
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(adjusted_mode->crtc_hdisplay - 1) |
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((adjusted_mode->crtc_htotal - 1) << 16));
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I915_WRITE(HBLANK(pipe),
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(adjusted_mode->crtc_hblank_start - 1) |
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((adjusted_mode->crtc_hblank_end - 1) << 16));
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I915_WRITE(HSYNC(pipe),
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(adjusted_mode->crtc_hsync_start - 1) |
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((adjusted_mode->crtc_hsync_end - 1) << 16));
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I915_WRITE(VTOTAL(pipe),
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(adjusted_mode->crtc_vdisplay - 1) |
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((adjusted_mode->crtc_vtotal - 1) << 16));
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I915_WRITE(VBLANK(pipe),
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(adjusted_mode->crtc_vblank_start - 1) |
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((adjusted_mode->crtc_vblank_end - 1) << 16));
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I915_WRITE(VSYNC(pipe),
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(adjusted_mode->crtc_vsync_start - 1) |
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((adjusted_mode->crtc_vsync_end - 1) << 16));
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/* pipesrc controls the size that is scaled from, which should
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* always be the user's requested size.
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*/
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I915_WRITE(PIPESRC(pipe),
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((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
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}
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static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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@ -4303,7 +4352,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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int plane = intel_crtc->plane;
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int refclk, num_connectors = 0;
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intel_clock_t clock, reduced_clock;
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u32 dspcntr, pipeconf, vsyncshift;
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u32 dspcntr, pipeconf;
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bool ok, has_reduced_clock = false, is_sdvo = false;
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bool is_lvds = false, is_tv = false, is_dp = false;
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struct intel_encoder *encoder;
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@ -4438,40 +4487,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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pipeconf &= ~PIPECONF_INTERLACE_MASK;
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if (!IS_GEN2(dev) &&
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adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
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adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
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/* the chip adds 2 halflines automatically */
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adjusted_mode->crtc_vtotal -= 1;
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adjusted_mode->crtc_vblank_end -= 1;
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vsyncshift = adjusted_mode->crtc_hsync_start
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- adjusted_mode->crtc_htotal/2;
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} else {
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else
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pipeconf |= PIPECONF_PROGRESSIVE;
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vsyncshift = 0;
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}
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if (!IS_GEN3(dev))
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I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
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I915_WRITE(HTOTAL(pipe),
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(adjusted_mode->crtc_hdisplay - 1) |
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((adjusted_mode->crtc_htotal - 1) << 16));
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I915_WRITE(HBLANK(pipe),
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(adjusted_mode->crtc_hblank_start - 1) |
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((adjusted_mode->crtc_hblank_end - 1) << 16));
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I915_WRITE(HSYNC(pipe),
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(adjusted_mode->crtc_hsync_start - 1) |
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((adjusted_mode->crtc_hsync_end - 1) << 16));
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I915_WRITE(VTOTAL(pipe),
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(adjusted_mode->crtc_vdisplay - 1) |
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((adjusted_mode->crtc_vtotal - 1) << 16));
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I915_WRITE(VBLANK(pipe),
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(adjusted_mode->crtc_vblank_start - 1) |
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((adjusted_mode->crtc_vblank_end - 1) << 16));
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I915_WRITE(VSYNC(pipe),
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(adjusted_mode->crtc_vsync_start - 1) |
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((adjusted_mode->crtc_vsync_end - 1) << 16));
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intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
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/* pipesrc and dspsize control the size that is scaled from,
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* which should always be the user's requested size.
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@ -4480,8 +4501,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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((mode->vdisplay - 1) << 16) |
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(mode->hdisplay - 1));
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I915_WRITE(DSPPOS(plane), 0);
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I915_WRITE(PIPESRC(pipe),
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((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
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I915_WRITE(PIPECONF(pipe), pipeconf);
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POSTING_READ(PIPECONF(pipe));
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@ -5087,42 +5106,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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}
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}
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if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
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/* the chip adds 2 halflines automatically */
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adjusted_mode->crtc_vtotal -= 1;
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adjusted_mode->crtc_vblank_end -= 1;
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I915_WRITE(VSYNCSHIFT(pipe),
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adjusted_mode->crtc_hsync_start
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- adjusted_mode->crtc_htotal/2);
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} else {
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I915_WRITE(VSYNCSHIFT(pipe), 0);
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}
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I915_WRITE(HTOTAL(pipe),
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(adjusted_mode->crtc_hdisplay - 1) |
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((adjusted_mode->crtc_htotal - 1) << 16));
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I915_WRITE(HBLANK(pipe),
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(adjusted_mode->crtc_hblank_start - 1) |
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((adjusted_mode->crtc_hblank_end - 1) << 16));
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I915_WRITE(HSYNC(pipe),
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(adjusted_mode->crtc_hsync_start - 1) |
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((adjusted_mode->crtc_hsync_end - 1) << 16));
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I915_WRITE(VTOTAL(pipe),
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(adjusted_mode->crtc_vdisplay - 1) |
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((adjusted_mode->crtc_vtotal - 1) << 16));
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I915_WRITE(VBLANK(pipe),
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(adjusted_mode->crtc_vblank_start - 1) |
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((adjusted_mode->crtc_vblank_end - 1) << 16));
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I915_WRITE(VSYNC(pipe),
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(adjusted_mode->crtc_vsync_start - 1) |
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((adjusted_mode->crtc_vsync_end - 1) << 16));
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/* pipesrc controls the size that is scaled from, which should
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* always be the user's requested size.
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*/
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I915_WRITE(PIPESRC(pipe),
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((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
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intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
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ironlake_set_m_n(crtc, mode, adjusted_mode);
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