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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 16:56:54 +07:00
intel_scu_ipc: Propagate pointer to struct intel_scu_ipc_dev
As much as possible propagate a pointer to struct intel_scu_ipc_dev. There is no functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Darren Hart <dvhart@linux.intel.com>
This commit is contained in:
Andy Shevchenko
Darren Hart
parent
f63fbcee67
commit
b0b3f578a1
@ -118,28 +118,30 @@ static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
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static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
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/*
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* Send ipc command
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* Command Register (Write Only):
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* A write to this register results in an interrupt to the SCU core processor
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* Format:
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* |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
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*/
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static inline void ipc_command(u32 cmd) /* Send ipc command */
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static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
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{
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if (ipcdev.irq_mode) {
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reinit_completion(&ipcdev.cmd_complete);
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writel(cmd | IPC_IOC, ipcdev.ipc_base);
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if (scu->irq_mode) {
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reinit_completion(&scu->cmd_complete);
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writel(cmd | IPC_IOC, scu->ipc_base);
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}
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writel(cmd, ipcdev.ipc_base);
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writel(cmd, scu->ipc_base);
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}
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/*
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* Write ipc data
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* IPC Write Buffer (Write Only):
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* 16-byte buffer for sending data associated with IPC command to
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* SCU. Size of the data is specified in the IPC_COMMAND_REG register
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*/
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static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */
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static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
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{
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writel(data, ipcdev.ipc_base + 0x80 + offset);
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writel(data, scu->ipc_base + 0x80 + offset);
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}
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/*
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@ -149,35 +151,37 @@ static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */
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* Format:
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* |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
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*/
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static inline u8 ipc_read_status(void)
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static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
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{
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return __raw_readl(ipcdev.ipc_base + 0x04);
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return __raw_readl(scu->ipc_base + 0x04);
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}
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static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */
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/* Read ipc byte data */
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static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)
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{
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return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
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return readb(scu->ipc_base + IPC_READ_BUFFER + offset);
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}
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static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */
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/* Read ipc u32 data */
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static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
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{
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return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
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return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
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}
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/* Wait till scu status is busy */
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static inline int busy_loop(void)
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static inline int busy_loop(struct intel_scu_ipc_dev *scu)
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{
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u32 status = ipc_read_status();
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u32 status = ipc_read_status(scu);
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u32 loop_count = 100000;
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/* break if scu doesn't reset busy bit after huge retry */
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while ((status & BIT(0)) && --loop_count) {
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udelay(1); /* scu processing time is in few u secods */
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status = ipc_read_status();
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status = ipc_read_status(scu);
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}
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if (status & BIT(0)) {
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dev_err(&ipcdev.pdev->dev, "IPC timed out");
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dev_err(&scu->pdev->dev, "IPC timed out");
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return -ETIMEDOUT;
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}
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@ -188,31 +192,32 @@ static inline int busy_loop(void)
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}
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/* Wait till ipc ioc interrupt is received or timeout in 3 HZ */
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static inline int ipc_wait_for_interrupt(void)
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static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
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{
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int status;
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if (!wait_for_completion_timeout(&ipcdev.cmd_complete, 3 * HZ)) {
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struct device *dev = &ipcdev.pdev->dev;
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if (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {
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struct device *dev = &scu->pdev->dev;
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dev_err(dev, "IPC timed out\n");
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return -ETIMEDOUT;
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}
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status = ipc_read_status();
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status = ipc_read_status(scu);
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if (status & BIT(1))
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return -EIO;
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return 0;
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}
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static int intel_scu_ipc_check_status(void)
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static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
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{
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return ipcdev.irq_mode ? ipc_wait_for_interrupt() : busy_loop();
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return scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
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}
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/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
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static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
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{
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struct intel_scu_ipc_dev *scu = &ipcdev;
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int nc;
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u32 offset = 0;
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int err;
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@ -223,7 +228,7 @@ static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
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mutex_lock(&ipclock);
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if (ipcdev.pdev == NULL) {
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if (scu->pdev == NULL) {
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mutex_unlock(&ipclock);
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return -ENODEV;
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}
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@ -235,27 +240,27 @@ static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
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if (id == IPC_CMD_PCNTRL_R) {
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for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
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ipc_data_writel(wbuf[nc], offset);
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ipc_command((count * 2) << 16 | id << 12 | 0 << 8 | op);
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ipc_data_writel(scu, wbuf[nc], offset);
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ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
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} else if (id == IPC_CMD_PCNTRL_W) {
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for (nc = 0; nc < count; nc++, offset += 1)
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cbuf[offset] = data[nc];
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for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
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ipc_data_writel(wbuf[nc], offset);
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ipc_command((count * 3) << 16 | id << 12 | 0 << 8 | op);
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ipc_data_writel(scu, wbuf[nc], offset);
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ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
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} else if (id == IPC_CMD_PCNTRL_M) {
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cbuf[offset] = data[0];
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cbuf[offset + 1] = data[1];
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ipc_data_writel(wbuf[0], 0); /* Write wbuff */
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ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
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ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
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ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
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}
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err = intel_scu_ipc_check_status();
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err = intel_scu_ipc_check_status(scu);
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if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
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/* Workaround: values are read as 0 without memcpy_fromio */
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memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
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memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);
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for (nc = 0; nc < count; nc++)
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data[nc] = ipc_data_readb(nc);
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data[nc] = ipc_data_readb(scu, nc);
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}
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mutex_unlock(&ipclock);
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return err;
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@ -436,15 +441,16 @@ EXPORT_SYMBOL(intel_scu_ipc_update_register);
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*/
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int intel_scu_ipc_simple_command(int cmd, int sub)
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{
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struct intel_scu_ipc_dev *scu = &ipcdev;
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int err;
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mutex_lock(&ipclock);
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if (ipcdev.pdev == NULL) {
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if (scu->pdev == NULL) {
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mutex_unlock(&ipclock);
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return -ENODEV;
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}
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ipc_command(sub << 12 | cmd);
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err = intel_scu_ipc_check_status();
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ipc_command(scu, sub << 12 | cmd);
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err = intel_scu_ipc_check_status(scu);
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mutex_unlock(&ipclock);
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return err;
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}
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@ -465,23 +471,24 @@ EXPORT_SYMBOL(intel_scu_ipc_simple_command);
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int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
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u32 *out, int outlen)
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{
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struct intel_scu_ipc_dev *scu = &ipcdev;
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int i, err;
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mutex_lock(&ipclock);
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if (ipcdev.pdev == NULL) {
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if (scu->pdev == NULL) {
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mutex_unlock(&ipclock);
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return -ENODEV;
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}
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for (i = 0; i < inlen; i++)
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ipc_data_writel(*in++, 4 * i);
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ipc_data_writel(scu, *in++, 4 * i);
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ipc_command((inlen << 16) | (sub << 12) | cmd);
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err = intel_scu_ipc_check_status();
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ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
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err = intel_scu_ipc_check_status(scu);
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if (!err) {
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for (i = 0; i < outlen; i++)
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*out++ = ipc_data_readl(4 * i);
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*out++ = ipc_data_readl(scu, 4 * i);
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}
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mutex_unlock(&ipclock);
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@ -507,25 +514,26 @@ EXPORT_SYMBOL(intel_scu_ipc_command);
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*/
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int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
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{
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struct intel_scu_ipc_dev *scu = &ipcdev;
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u32 cmd = 0;
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mutex_lock(&ipclock);
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if (ipcdev.pdev == NULL) {
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if (scu->pdev == NULL) {
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mutex_unlock(&ipclock);
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return -ENODEV;
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}
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cmd = (addr >> 24) & 0xFF;
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if (cmd == IPC_I2C_READ) {
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writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
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writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
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/* Write not getting updated without delay */
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mdelay(1);
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*data = readl(ipcdev.i2c_base + I2C_DATA_ADDR);
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*data = readl(scu->i2c_base + I2C_DATA_ADDR);
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} else if (cmd == IPC_I2C_WRITE) {
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writel(*data, ipcdev.i2c_base + I2C_DATA_ADDR);
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writel(*data, scu->i2c_base + I2C_DATA_ADDR);
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mdelay(1);
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writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
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writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
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} else {
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dev_err(&ipcdev.pdev->dev,
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dev_err(&scu->pdev->dev,
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"intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
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mutex_unlock(&ipclock);
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@ -545,8 +553,10 @@ EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
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*/
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static irqreturn_t ioc(int irq, void *dev_id)
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{
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if (ipcdev.irq_mode)
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complete(&ipcdev.cmd_complete);
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struct intel_scu_ipc_dev *scu = dev_id;
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if (scu->irq_mode)
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complete(&scu->cmd_complete);
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return IRQ_HANDLED;
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}
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@ -562,15 +572,16 @@ static irqreturn_t ioc(int irq, void *dev_id)
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static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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int err;
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struct intel_scu_ipc_dev *scu = &ipcdev;
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struct intel_scu_ipc_pdata_t *pdata;
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if (ipcdev.pdev) /* We support only one SCU */
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if (scu->pdev) /* We support only one SCU */
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return -EBUSY;
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pdata = (struct intel_scu_ipc_pdata_t *)id->driver_data;
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ipcdev.pdev = pci_dev_get(dev);
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ipcdev.irq_mode = pdata->irq_mode;
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scu->pdev = pci_dev_get(dev);
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scu->irq_mode = pdata->irq_mode;
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err = pcim_enable_device(dev);
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if (err)
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@ -580,21 +591,22 @@ static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
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if (err)
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return err;
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init_completion(&ipcdev.cmd_complete);
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init_completion(&scu->cmd_complete);
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err = devm_request_irq(&dev->dev, dev->irq, ioc, 0, "intel_scu_ipc",
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&ipcdev);
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scu);
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if (err)
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return err;
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ipcdev.ipc_base = pcim_iomap_table(dev)[0];
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scu->ipc_base = pcim_iomap_table(dev)[0];
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ipcdev.i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
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if (!ipcdev.i2c_base)
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scu->i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
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if (!scu->i2c_base)
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return -ENOMEM;
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intel_scu_devices_create();
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pci_set_drvdata(dev, scu);
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return 0;
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}
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@ -610,9 +622,11 @@ static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
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*/
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static void ipc_remove(struct pci_dev *pdev)
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{
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pci_dev_put(ipcdev.pdev);
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iounmap(ipcdev.i2c_base);
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ipcdev.pdev = NULL;
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struct intel_scu_ipc_dev *scu = pci_get_drvdata(pdev);
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pci_dev_put(scu->pdev);
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scu->pdev = NULL;
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iounmap(scu->i2c_base);
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intel_scu_devices_destroy();
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}
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