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drm/i915/execlists: Verify context register state before execution
Check that the context's ring register state still matches our expectations prior to execution. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191102125739.24626-1-chris@chris-wilson.co.uk
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@ -990,6 +990,58 @@ static void intel_engine_context_out(struct intel_engine_cs *engine)
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write_sequnlock_irqrestore(&engine->stats.lock, flags);
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write_sequnlock_irqrestore(&engine->stats.lock, flags);
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}
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}
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static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
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{
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if (INTEL_GEN(engine->i915) >= 12)
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return 0x60;
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else if (INTEL_GEN(engine->i915) >= 9)
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return 0x54;
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else if (engine->class == RENDER_CLASS)
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return 0x58;
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else
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return -1;
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}
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static void
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execlists_check_context(const struct intel_context *ce,
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const struct intel_engine_cs *engine)
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{
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const struct intel_ring *ring = ce->ring;
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u32 *regs = ce->lrc_reg_state;
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bool valid = true;
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int x;
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if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) {
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pr_err("%s: context submitted with incorrect RING_START [%08x], expected %08x\n",
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engine->name,
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regs[CTX_RING_START],
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i915_ggtt_offset(ring->vma));
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regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
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valid = false;
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}
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if ((regs[CTX_RING_CTL] & ~(RING_WAIT | RING_WAIT_SEMAPHORE)) !=
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(RING_CTL_SIZE(ring->size) | RING_VALID)) {
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pr_err("%s: context submitted with incorrect RING_CTL [%08x], expected %08x\n",
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engine->name,
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regs[CTX_RING_CTL],
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(u32)(RING_CTL_SIZE(ring->size) | RING_VALID));
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regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
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valid = false;
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}
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x = lrc_ring_mi_mode(engine);
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if (x != -1 && regs[x + 1] & (regs[x + 1] >> 16) & STOP_RING) {
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pr_err("%s: context submitted with STOP_RING [%08x] in RING_MI_MODE\n",
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engine->name, regs[x + 1]);
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regs[x + 1] &= ~STOP_RING;
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regs[x + 1] |= STOP_RING << 16;
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valid = false;
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}
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WARN_ONCE(!valid, "Invalid lrc state found before submission\n");
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}
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static inline struct intel_engine_cs *
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static inline struct intel_engine_cs *
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__execlists_schedule_in(struct i915_request *rq)
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__execlists_schedule_in(struct i915_request *rq)
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{
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{
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@ -998,6 +1050,9 @@ __execlists_schedule_in(struct i915_request *rq)
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intel_context_get(ce);
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intel_context_get(ce);
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if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
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execlists_check_context(ce, rq->engine);
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if (ce->tag) {
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if (ce->tag) {
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/* Use a fixed tag for OA and friends */
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/* Use a fixed tag for OA and friends */
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ce->lrc_desc |= (u64)ce->tag << 32;
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ce->lrc_desc |= (u64)ce->tag << 32;
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@ -2353,7 +2408,7 @@ __execlists_update_reg_state(const struct intel_context *ce,
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GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
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GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
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GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
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GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
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regs[CTX_RING_BUFFER_START] = i915_ggtt_offset(ring->vma);
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regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
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regs[CTX_RING_HEAD] = ring->head;
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regs[CTX_RING_HEAD] = ring->head;
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regs[CTX_RING_TAIL] = ring->tail;
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regs[CTX_RING_TAIL] = ring->tail;
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@ -2940,18 +2995,6 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
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&execlists->csb_status[reset_value]);
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&execlists->csb_status[reset_value]);
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}
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}
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static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
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{
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if (INTEL_GEN(engine->i915) >= 12)
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return 0x60;
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else if (INTEL_GEN(engine->i915) >= 9)
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return 0x54;
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else if (engine->class == RENDER_CLASS)
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return 0x58;
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else
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return -1;
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}
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static void __execlists_reset_reg_state(const struct intel_context *ce,
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static void __execlists_reset_reg_state(const struct intel_context *ce,
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const struct intel_engine_cs *engine)
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const struct intel_engine_cs *engine)
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{
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{
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@ -3885,7 +3928,7 @@ static void init_common_reg_state(u32 * const regs,
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_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
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_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
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CTX_CTRL_RS_CTX_ENABLE);
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CTX_CTRL_RS_CTX_ENABLE);
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regs[CTX_RING_BUFFER_CONTROL] = RING_CTL_SIZE(ring->size) | RING_VALID;
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regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
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regs[CTX_BB_STATE] = RING_BB_PPGTT;
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regs[CTX_BB_STATE] = RING_BB_PPGTT;
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}
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}
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@ -13,8 +13,8 @@
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#define CTX_CONTEXT_CONTROL (0x02 + 1)
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#define CTX_CONTEXT_CONTROL (0x02 + 1)
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#define CTX_RING_HEAD (0x04 + 1)
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#define CTX_RING_HEAD (0x04 + 1)
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#define CTX_RING_TAIL (0x06 + 1)
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#define CTX_RING_TAIL (0x06 + 1)
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#define CTX_RING_BUFFER_START (0x08 + 1)
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#define CTX_RING_START (0x08 + 1)
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#define CTX_RING_BUFFER_CONTROL (0x0a + 1)
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#define CTX_RING_CTL (0x0a + 1)
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#define CTX_BB_STATE (0x10 + 1)
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#define CTX_BB_STATE (0x10 + 1)
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#define CTX_BB_PER_CTX_PTR (0x18 + 1)
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#define CTX_BB_PER_CTX_PTR (0x18 + 1)
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#define CTX_PDP3_UDW (0x24 + 1)
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#define CTX_PDP3_UDW (0x24 + 1)
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@ -3207,12 +3207,12 @@ static int live_lrc_fixed(void *arg)
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} tbl[] = {
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} tbl[] = {
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{
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{
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i915_mmio_reg_offset(RING_START(engine->mmio_base)),
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i915_mmio_reg_offset(RING_START(engine->mmio_base)),
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CTX_RING_BUFFER_START - 1,
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CTX_RING_START - 1,
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"RING_START"
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"RING_START"
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},
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},
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{
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{
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i915_mmio_reg_offset(RING_CTL(engine->mmio_base)),
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i915_mmio_reg_offset(RING_CTL(engine->mmio_base)),
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CTX_RING_BUFFER_CONTROL - 1,
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CTX_RING_CTL - 1,
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"RING_CTL"
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"RING_CTL"
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},
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},
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{
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{
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@ -3231,7 +3231,7 @@ static int live_lrc_fixed(void *arg)
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"RING_MI_MODE"
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"RING_MI_MODE"
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},
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},
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{
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{
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engine->mmio_base + 0x110,
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i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)),
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CTX_BB_STATE - 1,
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CTX_BB_STATE - 1,
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"BB_STATE"
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"BB_STATE"
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},
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},
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