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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ARM: 6459/2: sa1100: Add nanoEngine PCI support.
This patch adds nanoEngine's PCI support. Signed-off-by: Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Marcelo Roberto Jimenez
Russell King
parent
fa87672ab3
commit
b080ac8ad4
@ -1164,7 +1164,7 @@ config ISA_DMA_API
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bool
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config PCI
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bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
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bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX || SA1100_NANOENGINE
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help
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Find out whether you have a PCI motherboard. PCI is the name of a
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bus system, i.e. the way the CPU talks to the other stuff inside
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@ -1175,6 +1175,12 @@ config PCI_DOMAINS
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bool
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depends on PCI
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config PCI_NANOENGINE
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bool "BSE nanoEngine PCI support"
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depends on SA1100_NANOENGINE
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help
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Enable PCI on the BSE nanoEngine board.
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config PCI_SYSCALL
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def_bool PCI
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@ -121,6 +121,8 @@ config SA1100_LART
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config SA1100_NANOENGINE
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bool "nanoEngine"
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select CPU_FREQ_SA1110
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select PCI
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select PCI_NANOENGINE
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help
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Say Y here if you are using the Bright Star Engineering nanoEngine.
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See <http://www.brightstareng.com/arm/nanoeng.htm> for information
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@ -38,6 +38,7 @@ obj-$(CONFIG_SA1100_LART) += lart.o
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led-$(CONFIG_SA1100_LART) += leds-lart.o
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obj-$(CONFIG_SA1100_NANOENGINE) += nanoengine.o
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obj-$(CONFIG_PCI_NANOENGINE) += pci-nanoengine.o
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obj-$(CONFIG_SA1100_PLEB) += pleb.o
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@ -76,4 +76,12 @@ static inline unsigned long get_clock_tick_rate(void)
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#include "SA-1101.h"
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#endif
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#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_PCI)
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#define PCIBIOS_MIN_IO 0
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#define PCIBIOS_MIN_MEM 0
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#define pcibios_assign_all_busses() 1
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#define HAVE_ARCH_PCI_SET_DMA_MASK 1
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#endif
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#endif /* _ASM_ARCH_HARDWARE_H */
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@ -14,6 +14,8 @@
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#ifndef __ASM_ARCH_NANOENGINE_H
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#define __ASM_ARCH_NANOENGINE_H
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#include <mach/irqs.h>
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#define GPIO_PC_READY0 GPIO_GPIO(11) /* ready for socket 0 (active high)*/
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#define GPIO_PC_READY1 GPIO_GPIO(12) /* ready for socket 1 (active high) */
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#define GPIO_PC_CD0 GPIO_GPIO(13) /* detect for socket 0 (active low) */
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@ -21,10 +23,30 @@
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#define GPIO_PC_RESET0 GPIO_GPIO(15) /* reset socket 0 */
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#define GPIO_PC_RESET1 GPIO_GPIO(16) /* reset socket 1 */
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#define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0
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#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11
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#define NANOENGINE_IRQ_GPIO_PC_READY1 IRQ_GPIO12
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#define NANOENGINE_IRQ_GPIO_PC_CD0 IRQ_GPIO13
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#define NANOENGINE_IRQ_GPIO_PC_CD1 IRQ_GPIO14
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/*
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* nanoEngine Memory Map:
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*
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* 0000.0000 - 003F.0000 - 4 MB Flash
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* C000.0000 - C1FF.FFFF - 32 MB SDRAM
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* 1860.0000 - 186F.FFFF - 1 MB Internal PCI Memory Read/Write
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* 18A1.0000 - 18A1.FFFF - 64 KB Internal PCI Config Space
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* 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode
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* 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode
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*
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*/
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#define NANO_PCI_MEM_RW_PHYS 0x18600000
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#define NANO_PCI_MEM_RW_VIRT 0xf1000000
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#define NANO_PCI_MEM_RW_SIZE SZ_1M
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#define NANO_PCI_CONFIG_SPACE_PHYS 0x18A10000
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#define NANO_PCI_CONFIG_SPACE_VIRT 0xf2000000
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#define NANO_PCI_CONFIG_SPACE_SIZE SZ_64K
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#endif
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@ -26,6 +26,7 @@
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#include <asm/mach/serial_sa1100.h>
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#include <mach/hardware.h>
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#include <mach/nanoengine.h>
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#include "generic.h"
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@ -74,11 +75,17 @@ static struct map_desc nanoengine_io_desc[] __initdata = {
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.pfn = __phys_to_pfn(0x10000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, {
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/* Internal PCI Memory Read/Write */
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.virtual = NANO_PCI_MEM_RW_VIRT,
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.pfn = __phys_to_pfn(NANO_PCI_MEM_RW_PHYS),
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.length = NANO_PCI_MEM_RW_SIZE,
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.type = MT_DEVICE
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}, {
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/* Internal PCI Config Space */
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.virtual = 0xf1000000,
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.pfn = __phys_to_pfn(0x18A00000),
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.length = 0x00100000,
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.virtual = NANO_PCI_CONFIG_SPACE_VIRT,
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.pfn = __phys_to_pfn(NANO_PCI_CONFIG_SPACE_PHYS),
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.length = NANO_PCI_CONFIG_SPACE_SIZE,
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.type = MT_DEVICE
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}
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};
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284
arch/arm/mach-sa1100/pci-nanoengine.c
Normal file
284
arch/arm/mach-sa1100/pci-nanoengine.c
Normal file
@ -0,0 +1,284 @@
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/*
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* linux/arch/arm/mach-sa1100/pci-nanoengine.c
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*
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* PCI functions for BSE nanoEngine PCI
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*
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* Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <asm/mach/pci.h>
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#include <asm/mach-types.h>
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#include <mach/nanoengine.h>
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static DEFINE_SPINLOCK(nano_lock);
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static int nanoengine_get_pci_address(struct pci_bus *bus,
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unsigned int devfn, int where, unsigned long *address)
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{
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int ret = PCIBIOS_DEVICE_NOT_FOUND;
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unsigned int busnr = bus->number;
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*address = NANO_PCI_CONFIG_SPACE_VIRT +
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((bus->number << 16) | (devfn << 8) | (where & ~3));
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ret = (busnr > 255 || devfn > 255 || where > 255) ?
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PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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return ret;
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}
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static int nanoengine_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *val)
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{
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int ret;
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unsigned long address;
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unsigned long flags;
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u32 v;
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/* nanoEngine PCI bridge does not return -1 for a non-existing
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* device. We must fake the answer. We know that the only valid
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* device is device zero at bus 0, which is the network chip. */
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if (bus->number != 0 || (devfn >> 3) != 0) {
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v = -1;
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nanoengine_get_pci_address(bus, devfn, where, &address);
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goto exit_function;
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}
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spin_lock_irqsave(&nano_lock, flags);
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ret = nanoengine_get_pci_address(bus, devfn, where, &address);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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v = __raw_readl(address);
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spin_unlock_irqrestore(&nano_lock, flags);
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v >>= ((where & 3) * 8);
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v &= (unsigned long)(-1) >> ((4 - size) * 8);
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exit_function:
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*val = v;
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return PCIBIOS_SUCCESSFUL;
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}
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static int nanoengine_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 val)
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{
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int ret;
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unsigned long address;
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unsigned long flags;
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unsigned shift;
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u32 v;
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shift = (where & 3) * 8;
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spin_lock_irqsave(&nano_lock, flags);
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ret = nanoengine_get_pci_address(bus, devfn, where, &address);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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v = __raw_readl(address);
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switch (size) {
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case 1:
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v &= ~(0xFF << shift);
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v |= val << shift;
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break;
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case 2:
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v &= ~(0xFFFF << shift);
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v |= val << shift;
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break;
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case 4:
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v = val;
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break;
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}
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__raw_writel(v, address);
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spin_unlock_irqrestore(&nano_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops pci_nano_ops = {
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.read = nanoengine_read_config,
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.write = nanoengine_write_config,
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};
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static int __init pci_nanoengine_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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return NANOENGINE_IRQ_GPIO_PCI;
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}
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struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys)
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{
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return pci_scan_bus(sys->busnr, &pci_nano_ops, sys);
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}
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static struct resource pci_io_ports = {
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.name = "PCI IO",
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.start = 0x400,
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.end = 0x7FF,
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.flags = IORESOURCE_IO,
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};
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static struct resource pci_non_prefetchable_memory = {
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.name = "PCI non-prefetchable",
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.start = NANO_PCI_MEM_RW_PHYS,
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/* nanoEngine documentation says there is a 1 Megabyte window here,
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* but PCI reports just 128 + 8 kbytes. */
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.end = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1,
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/* .end = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/
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.flags = IORESOURCE_MEM,
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};
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/*
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* nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it
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* overlaps with previously defined memory.
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*
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* Here is what happens:
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*
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# dmesg
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...
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pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
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pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
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pci 0000:00:00.0: reg 14: [io 0x0000-0x003f]
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pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
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pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
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pci 0000:00:00.0: supports D1 D2
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pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
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pci 0000:00:00.0: PME# disabled
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PCI: bus0: Fast back to back transfers enabled
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pci 0000:00:00.0: BAR 6: can't assign mem pref (size 0x100000)
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pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
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pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
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pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
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pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
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pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f]
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pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f])
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*
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* On the other hand, if we do not request the prefetchable memory resource,
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* linux will alloc it first and the two non-prefetchable memory areas that
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* are our real interest will not be mapped. So we choose to map it to an
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* unused area. It gets recognized as expansion ROM, but becomes disabled.
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*
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* Here is what happens then:
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*
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# dmesg
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...
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pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
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pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
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pci 0000:00:00.0: reg 14: [io 0x0000-0x003f]
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pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
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pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
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pci 0000:00:00.0: supports D1 D2
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pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
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pci 0000:00:00.0: PME# disabled
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PCI: bus0: Fast back to back transfers enabled
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pci 0000:00:00.0: BAR 6: assigned [mem 0x78000000-0x780fffff pref]
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pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
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pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
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pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
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pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
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pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f]
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pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f])
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# lspci -vv -s 0000:00:00.0
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00:00.0 Class 0200: Device 8086:1209 (rev 09)
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Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
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Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR+ <PERR+ INTx-
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Latency: 0 (2000ns min, 14000ns max), Cache Line Size: 32 bytes
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Interrupt: pin A routed to IRQ 0
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Region 0: Memory at 18620000 (32-bit, non-prefetchable) [size=4K]
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Region 1: I/O ports at 0400 [size=64]
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Region 2: [virtual] Memory at 18600000 (32-bit, non-prefetchable) [size=128K]
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[virtual] Expansion ROM at 78000000 [disabled] [size=1M]
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Capabilities: [dc] Power Management version 2
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Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
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Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME-
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Kernel driver in use: e100
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Kernel modules: e100
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*
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*/
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static struct resource pci_prefetchable_memory = {
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.name = "PCI prefetchable",
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.start = 0x78000000,
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.end = 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
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};
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static int __init pci_nanoengine_setup_resources(struct resource **resource)
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{
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if (request_resource(&ioport_resource, &pci_io_ports)) {
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printk(KERN_ERR "PCI: unable to allocate io port region\n");
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return -EBUSY;
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}
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if (request_resource(&iomem_resource, &pci_non_prefetchable_memory)) {
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release_resource(&pci_io_ports);
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printk(KERN_ERR "PCI: unable to allocate non prefetchable\n");
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return -EBUSY;
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}
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if (request_resource(&iomem_resource, &pci_prefetchable_memory)) {
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release_resource(&pci_io_ports);
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release_resource(&pci_non_prefetchable_memory);
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printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
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return -EBUSY;
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}
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resource[0] = &pci_io_ports;
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resource[1] = &pci_non_prefetchable_memory;
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resource[2] = &pci_prefetchable_memory;
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return 1;
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}
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int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
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{
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int ret = 0;
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if (nr == 0) {
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sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
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sys->io_offset = 0x400;
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ret = pci_nanoengine_setup_resources(sys->resource);
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/* Enable alternate memory bus master mode, see
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* "Intel StrongARM SA1110 Developer's Manual",
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* section 10.8, "Alternate Memory Bus Master Mode". */
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GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
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GAFR |= GPIO_MBGNT | GPIO_MBREQ;
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TUCR |= TUCR_MBGPIO;
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}
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return ret;
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}
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static struct hw_pci nanoengine_pci __initdata = {
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.map_irq = pci_nanoengine_map_irq,
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.nr_controllers = 1,
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.scan = pci_nanoengine_scan_bus,
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.setup = pci_nanoengine_setup,
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};
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static int __init nanoengine_pci_init(void)
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{
|
||||
if (machine_is_nanoengine())
|
||||
pci_common_init(&nanoengine_pci);
|
||||
return 0;
|
||||
}
|
||||
|
||||
subsys_initcall(nanoengine_pci_init);
|
||||
Loading…
Reference in New Issue
Block a user