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irqchip: Add TB10x interrupt controller driver
The SOC interrupt controller driver for the Abilis Systems TB10x series of SOCs based on ARC700 CPUs. Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com> Signed-off-by: Pierrick Hascoet <pierrick.hascoet@abilis.com> Cc: Vineet Gupta <Vineet.Gupta1@synopsys.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Cc: devicetree-discuss@lists.ozlabs.org Link: http://lkml.kernel.org/r/1372177797-9458-1-git-send-email-christian.ruppert@abilis.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Christian Ruppert
Thomas Gleixner
parent
fbab62c5cd
commit
b06eb0173e
@ -0,0 +1,38 @@
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TB10x Top Level Interrupt Controller
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====================================
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The Abilis TB10x SOC contains a custom interrupt controller. It performs
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one-to-one mapping of external interrupt sources to CPU interrupts and
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provides support for reconfigurable trigger modes.
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Required properties
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-------------------
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- compatible: Should be "abilis,tb10x-ictl"
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- reg: specifies physical base address and size of register range.
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- interrupt-congroller: Identifies the node as an interrupt controller.
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- #interrupt cells: Specifies the number of cells used to encode an interrupt
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source connected to this controller. The value shall be 2.
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- interrupt-parent: Specifies the parent interrupt controller.
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- interrupts: Specifies the list of interrupt lines which are handled by
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the interrupt controller in the parent controller's notation. Interrupts
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are mapped one-to-one to parent interrupts.
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Example
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-------
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intc: interrupt-controller { /* Parent interrupt controller */
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interrupt-controller;
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#interrupt-cells = <1>; /* For example below */
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/* ... */
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};
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tb10x_ictl: pic@2000 { /* TB10x interrupt controller */
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compatible = "abilis,tb10x-ictl";
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reg = <0x2000 0x20>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
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20 21 22 23 24 25 26 27 28 29 30 31>;
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};
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@ -38,6 +38,11 @@ config RENESAS_IRQC
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bool
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select IRQ_DOMAIN
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config TB10X_IRQC
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config VERSATILE_FPGA_IRQ
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bool
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select IRQ_DOMAIN
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@ -17,3 +17,4 @@ obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
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obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
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obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
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obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o
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obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
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195
drivers/irqchip/irq-tb10x.c
Normal file
195
drivers/irqchip/irq-tb10x.c
Normal file
@ -0,0 +1,195 @@
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/*
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* Abilis Systems interrupt controller driver
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*
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* Copyright (C) Abilis Systems 2012
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*
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* Author: Christian Ruppert <christian.ruppert@abilis.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/bitops.h>
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#include "irqchip.h"
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#define AB_IRQCTL_INT_ENABLE 0x00
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#define AB_IRQCTL_INT_STATUS 0x04
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#define AB_IRQCTL_SRC_MODE 0x08
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#define AB_IRQCTL_SRC_POLARITY 0x0C
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#define AB_IRQCTL_INT_MODE 0x10
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#define AB_IRQCTL_INT_POLARITY 0x14
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#define AB_IRQCTL_INT_FORCE 0x18
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#define AB_IRQCTL_MAXIRQ 32
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static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg,
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u32 val)
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{
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irq_reg_writel(val, gc->reg_base + reg);
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}
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static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg)
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{
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return irq_reg_readl(gc->reg_base + reg);
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}
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static int tb10x_irq_set_type(struct irq_data *data, unsigned int flow_type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
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uint32_t im, mod, pol;
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im = data->mask;
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irq_gc_lock(gc);
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mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im;
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pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im;
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switch (flow_type & IRQF_TRIGGER_MASK) {
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case IRQ_TYPE_EDGE_FALLING:
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pol ^= im;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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mod ^= im;
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break;
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case IRQ_TYPE_NONE:
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flow_type = IRQ_TYPE_LEVEL_LOW;
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case IRQ_TYPE_LEVEL_LOW:
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mod ^= im;
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pol ^= im;
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break;
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case IRQ_TYPE_EDGE_RISING:
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break;
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default:
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irq_gc_unlock(gc);
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pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",
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__func__, data->irq);
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return -EBADR;
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}
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irqd_set_trigger_type(data, flow_type);
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irq_setup_alt_chip(data, flow_type);
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ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod);
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ab_irqctl_writereg(gc, AB_IRQCTL_SRC_POLARITY, pol);
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ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, im);
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irq_gc_unlock(gc);
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return IRQ_SET_MASK_OK;
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}
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static void tb10x_irq_cascade(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_domain *domain = irq_desc_get_handler_data(desc);
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generic_handle_irq(irq_find_mapping(domain, irq));
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}
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static int __init of_tb10x_init_irq(struct device_node *ictl,
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struct device_node *parent)
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{
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int i, ret, nrirqs = of_irq_count(ictl);
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struct resource mem;
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struct irq_chip_generic *gc;
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struct irq_domain *domain;
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void __iomem *reg_base;
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if (of_address_to_resource(ictl, 0, &mem)) {
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pr_err("%s: No registers declared in DeviceTree.\n",
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ictl->name);
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return -EINVAL;
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}
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if (!request_mem_region(mem.start, resource_size(&mem),
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ictl->name)) {
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pr_err("%s: Request mem region failed.\n", ictl->name);
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return -EBUSY;
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}
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reg_base = ioremap(mem.start, resource_size(&mem));
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if (!reg_base) {
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ret = -EBUSY;
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pr_err("%s: ioremap failed.\n", ictl->name);
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goto ioremap_fail;
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}
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domain = irq_domain_add_linear(ictl, AB_IRQCTL_MAXIRQ,
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&irq_generic_chip_ops, NULL);
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if (!domain) {
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ret = -ENOMEM;
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pr_err("%s: Could not register interrupt domain.\n",
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ictl->name);
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goto irq_domain_add_fail;
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}
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ret = irq_alloc_domain_generic_chips(domain, AB_IRQCTL_MAXIRQ,
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2, ictl->name, handle_level_irq,
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IRQ_NOREQUEST, IRQ_NOPROBE,
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IRQ_GC_INIT_MASK_CACHE);
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if (ret) {
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pr_err("%s: Could not allocate generic interrupt chip.\n",
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ictl->name);
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goto gc_alloc_fail;
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}
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gc = domain->gc->gc[0];
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gc->reg_base = reg_base;
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gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
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gc->chip_types[0].chip.irq_set_type = tb10x_irq_set_type;
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gc->chip_types[0].regs.mask = AB_IRQCTL_INT_ENABLE;
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gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
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gc->chip_types[1].chip.name = gc->chip_types[0].chip.name;
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gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
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gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
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gc->chip_types[1].chip.irq_set_type = tb10x_irq_set_type;
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gc->chip_types[1].regs.ack = AB_IRQCTL_INT_STATUS;
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gc->chip_types[1].regs.mask = AB_IRQCTL_INT_ENABLE;
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gc->chip_types[1].handler = handle_edge_irq;
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for (i = 0; i < nrirqs; i++) {
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unsigned int irq = irq_of_parse_and_map(ictl, i);
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irq_set_handler_data(irq, domain);
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irq_set_chained_handler(irq, tb10x_irq_cascade);
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}
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ab_irqctl_writereg(gc, AB_IRQCTL_INT_ENABLE, 0);
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ab_irqctl_writereg(gc, AB_IRQCTL_INT_MODE, 0);
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ab_irqctl_writereg(gc, AB_IRQCTL_INT_POLARITY, 0);
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ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, ~0UL);
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return 0;
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gc_alloc_fail:
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irq_domain_remove(domain);
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irq_domain_add_fail:
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iounmap(reg_base);
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ioremap_fail:
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release_mem_region(mem.start, resource_size(&mem));
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return ret;
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}
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IRQCHIP_DECLARE(tb10x_intc, "abilis,tb10x-ictl", of_tb10x_init_irq);
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