mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 09:17:00 +07:00
iwlwifi: configure the queues from the op_mode
Since the op_mode defines the queue mapping, let it do it completely through the API functions. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
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@ -190,6 +190,44 @@ enum {
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REPLY_MAX = 0xff
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};
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/*
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* Minimum number of queues. MAX_NUM is defined in hw specific files.
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* Set the minimum to accommodate
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* - 4 standard TX queues
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* - the command queue
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* - 4 PAN TX queues
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* - the PAN multicast queue, and
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* - the AUX (TX during scan dwell) queue.
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*/
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#define IWL_MIN_NUM_QUEUES 11
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/*
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* Command queue depends on iPAN support.
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*/
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#define IWL_DEFAULT_CMD_QUEUE_NUM 4
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#define IWL_IPAN_CMD_QUEUE_NUM 9
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#define IWL_TX_FIFO_BK 0 /* shared */
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#define IWL_TX_FIFO_BE 1
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#define IWL_TX_FIFO_VI 2 /* shared */
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#define IWL_TX_FIFO_VO 3
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#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
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#define IWL_TX_FIFO_BE_IPAN 4
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#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
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#define IWL_TX_FIFO_VO_IPAN 5
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/* re-uses the VO FIFO, uCode will properly flush/schedule */
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#define IWL_TX_FIFO_AUX 5
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#define IWL_TX_FIFO_UNUSED 255
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#define IWLAGN_CMD_FIFO_NUM 7
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/*
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* This queue number is required for proper operation
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* because the ucode will stop/start the scheduler as
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* required.
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*/
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#define IWL_IPAN_MCAST_QUEUE 8
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/******************************************************************************
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* (0)
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* Commonly used structures and definitions:
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@ -755,8 +793,6 @@ struct iwl_qosparam_cmd {
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#define IWLAGN_BROADCAST_ID 15
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#define IWLAGN_STATION_COUNT 16
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#define IWL_INVALID_STATION 255
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#define IWL_MAX_TID_COUNT 8
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#define IWL_TID_NON_QOS IWL_MAX_TID_COUNT
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#define STA_FLG_TX_RATE_MSK cpu_to_le32(1 << 2)
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@ -90,22 +90,6 @@
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#define IWL_NUM_SCAN_RATES (2)
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/*
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* Minimum number of queues. MAX_NUM is defined in hw specific files.
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* Set the minimum to accommodate
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* - 4 standard TX queues
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* - the command queue
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* - 4 PAN TX queues
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* - the PAN multicast queue, and
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* - the AUX (TX during scan dwell) queue.
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*/
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#define IWL_MIN_NUM_QUEUES 11
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/*
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* Command queue depends on iPAN support.
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*/
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#define IWL_DEFAULT_CMD_QUEUE_NUM 4
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#define IWL_IPAN_CMD_QUEUE_NUM 9
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#define IEEE80211_DATA_LEN 2304
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#define IEEE80211_4ADDR_LEN 30
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@ -518,49 +518,6 @@ static void iwl_bg_tx_flush(struct work_struct *work)
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* queue/FIFO/AC mapping definitions
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*/
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#define IWL_TX_FIFO_BK 0 /* shared */
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#define IWL_TX_FIFO_BE 1
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#define IWL_TX_FIFO_VI 2 /* shared */
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#define IWL_TX_FIFO_VO 3
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#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
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#define IWL_TX_FIFO_BE_IPAN 4
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#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
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#define IWL_TX_FIFO_VO_IPAN 5
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/* re-uses the VO FIFO, uCode will properly flush/schedule */
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#define IWL_TX_FIFO_AUX 5
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#define IWL_TX_FIFO_UNUSED -1
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#define IWLAGN_CMD_FIFO_NUM 7
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/*
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* This queue number is required for proper operation
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* because the ucode will stop/start the scheduler as
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* required.
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*/
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#define IWL_IPAN_MCAST_QUEUE 8
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static const u8 iwlagn_default_queue_to_tx_fifo[] = {
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IWL_TX_FIFO_VO,
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IWL_TX_FIFO_VI,
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IWL_TX_FIFO_BE,
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IWL_TX_FIFO_BK,
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IWLAGN_CMD_FIFO_NUM,
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};
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static const u8 iwlagn_ipan_queue_to_tx_fifo[] = {
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IWL_TX_FIFO_VO,
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IWL_TX_FIFO_VI,
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IWL_TX_FIFO_BE,
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IWL_TX_FIFO_BK,
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IWL_TX_FIFO_BK_IPAN,
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IWL_TX_FIFO_BE_IPAN,
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IWL_TX_FIFO_VI_IPAN,
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IWL_TX_FIFO_VO_IPAN,
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IWL_TX_FIFO_BE_IPAN,
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IWLAGN_CMD_FIFO_NUM,
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IWL_TX_FIFO_AUX,
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};
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static const u8 iwlagn_bss_ac_to_fifo[] = {
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IWL_TX_FIFO_VO,
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IWL_TX_FIFO_VI,
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@ -1350,6 +1307,7 @@ static struct iwl_op_mode *iwl_op_mode_dvm_start(struct iwl_trans *trans,
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else
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trans_cfg.queue_watchdog_timeout = IWL_WATCHDOG_DISABLED;
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trans_cfg.command_names = iwl_dvm_cmd_strings;
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trans_cfg.cmd_fifo = IWLAGN_CMD_FIFO_NUM;
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WARN_ON(sizeof(priv->transport_queue_stop) * BITS_PER_BYTE <
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priv->cfg->base_params->num_of_queues);
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@ -1363,15 +1321,9 @@ static struct iwl_op_mode *iwl_op_mode_dvm_start(struct iwl_trans *trans,
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if (ucode_flags & IWL_UCODE_TLV_FLAGS_PAN) {
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priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
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trans_cfg.cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
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trans_cfg.queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
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trans_cfg.n_queue_to_fifo =
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ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo);
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} else {
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priv->sta_key_max_num = STA_KEY_MAX_NUM;
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trans_cfg.cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
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trans_cfg.queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
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trans_cfg.n_queue_to_fifo =
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ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo);
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}
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/* Configure transport layer */
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@ -1460,9 +1412,6 @@ static struct iwl_op_mode *iwl_op_mode_dvm_start(struct iwl_trans *trans,
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ucode_flags &= ~IWL_UCODE_TLV_FLAGS_P2P;
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priv->sta_key_max_num = STA_KEY_MAX_NUM;
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trans_cfg.cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
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trans_cfg.queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
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trans_cfg.n_queue_to_fifo =
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ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo);
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/* Configure transport layer again*/
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iwl_trans_configure(priv->trans, &trans_cfg);
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@ -1480,9 +1429,6 @@ static struct iwl_op_mode *iwl_op_mode_dvm_start(struct iwl_trans *trans,
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atomic_set(&priv->queue_stop_count[i], 0);
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}
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WARN_ON(trans_cfg.queue_to_fifo[trans_cfg.cmd_queue] !=
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IWLAGN_CMD_FIFO_NUM);
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if (iwl_init_drv(priv))
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goto out_free_eeprom;
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@ -226,13 +226,50 @@ int iwl_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
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return ret;
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}
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static const u8 iwlagn_default_queue_to_tx_fifo[] = {
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IWL_TX_FIFO_VO,
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IWL_TX_FIFO_VI,
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IWL_TX_FIFO_BE,
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IWL_TX_FIFO_BK,
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};
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static const u8 iwlagn_ipan_queue_to_tx_fifo[] = {
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IWL_TX_FIFO_VO,
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IWL_TX_FIFO_VI,
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IWL_TX_FIFO_BE,
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IWL_TX_FIFO_BK,
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IWL_TX_FIFO_BK_IPAN,
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IWL_TX_FIFO_BE_IPAN,
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IWL_TX_FIFO_VI_IPAN,
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IWL_TX_FIFO_VO_IPAN,
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IWL_TX_FIFO_BE_IPAN,
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IWL_TX_FIFO_UNUSED,
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IWL_TX_FIFO_AUX,
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};
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static int iwl_alive_notify(struct iwl_priv *priv)
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{
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const u8 *queue_to_txf;
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u8 n_queues;
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int ret;
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int i;
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iwl_trans_fw_alive(priv->trans);
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if (priv->fw->ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN &&
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priv->eeprom_data->sku & EEPROM_SKU_CAP_IPAN_ENABLE) {
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n_queues = ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo);
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queue_to_txf = iwlagn_ipan_queue_to_tx_fifo;
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} else {
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n_queues = ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo);
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queue_to_txf = iwlagn_default_queue_to_tx_fifo;
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}
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for (i = 0; i < n_queues; i++)
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if (queue_to_txf[i] != IWL_TX_FIFO_UNUSED)
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iwl_trans_ac_txq_enable(priv->trans, i,
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queue_to_txf[i]);
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priv->passive_no_rx = false;
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priv->transport_queue_stop = 0;
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@ -290,16 +290,17 @@ static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r)
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* currently supports
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*/
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#define IWL_MAX_HW_QUEUES 32
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#define IWL_INVALID_STATION 255
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#define IWL_MAX_TID_COUNT 8
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#define IWL_FRAME_LIMIT 64
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/**
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* struct iwl_trans_config - transport configuration
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*
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* @op_mode: pointer to the upper layer.
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* @queue_to_fifo: queue to FIFO mapping to set up by
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* default
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* @n_queue_to_fifo: number of queues to set up
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* @cmd_queue: the index of the command queue.
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* Must be set before start_fw.
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* @cmd_fifo: the fifo for host commands
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* @no_reclaim_cmds: Some devices erroneously don't set the
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* SEQ_RX_FRAME bit on some notifications, this is the
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* list of such notifications to filter. Max length is
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@ -314,10 +315,9 @@ static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r)
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*/
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struct iwl_trans_config {
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struct iwl_op_mode *op_mode;
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const u8 *queue_to_fifo;
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u8 n_queue_to_fifo;
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u8 cmd_queue;
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u8 cmd_fifo;
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const u8 *no_reclaim_cmds;
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int n_no_reclaim_cmds;
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@ -355,9 +355,9 @@ struct iwl_trans;
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* Must be atomic
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* @reclaim: free packet until ssn. Returns a list of freed packets.
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* Must be atomic
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* @txq_enable: setup a tx queue for AMPDU - will be called once the HW is
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* ready and a successful ADDBA response has been received.
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* May sleep
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* @txq_enable: setup a queue. To setup an AC queue, use the
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* iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before
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* this one. The op_mode must not configure the HCMD queue. May sleep.
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* @txq_disable: de-configure a Tx queue to send AMPDUs
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* Must be atomic
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* @wait_tx_queue_empty: wait until all tx queues are empty
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@ -497,9 +497,9 @@ static inline void iwl_trans_fw_alive(struct iwl_trans *trans)
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{
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might_sleep();
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trans->ops->fw_alive(trans);
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trans->state = IWL_TRANS_FW_ALIVE;
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trans->ops->fw_alive(trans);
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}
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static inline int iwl_trans_start_fw(struct iwl_trans *trans,
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@ -593,6 +593,13 @@ static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,
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frame_limit, ssn);
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}
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static inline void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue,
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int fifo)
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{
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iwl_trans_txq_enable(trans, queue, fifo, IWL_INVALID_STATION,
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IWL_MAX_TID_COUNT, IWL_FRAME_LIMIT, 0);
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}
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static inline int iwl_trans_wait_tx_queue_empty(struct iwl_trans *trans)
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{
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WARN_ONCE(trans->state != IWL_TRANS_FW_ALIVE,
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@ -269,10 +269,9 @@ struct iwl_trans_pcie {
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wait_queue_head_t ucode_write_waitq;
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unsigned long status;
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u8 cmd_queue;
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u8 cmd_fifo;
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u8 n_no_reclaim_cmds;
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u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
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u8 setup_q_to_fifo[IWL_MAX_HW_QUEUES];
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u8 n_q_to_fifo;
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bool rx_buf_size_8k;
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u32 rx_page_order;
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@ -1059,7 +1059,7 @@ static void iwl_tx_start(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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u32 a;
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int i, chan;
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int chan;
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u32 reg_val;
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/* make sure all queue are not stopped/used */
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@ -1091,12 +1091,8 @@ static void iwl_tx_start(struct iwl_trans *trans)
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*/
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iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
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for (i = 0; i < trans_pcie->n_q_to_fifo; i++) {
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int fifo = trans_pcie->setup_q_to_fifo[i];
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iwl_trans_pcie_txq_enable(trans, i, fifo, IWL_INVALID_STATION,
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IWL_TID_NON_QOS, SCD_FRAME_LIMIT, 0);
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}
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iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
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trans_pcie->cmd_fifo);
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/* Activate all Tx DMA/FIFO channels */
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iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
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@ -1528,6 +1524,7 @@ static void iwl_trans_pcie_configure(struct iwl_trans *trans,
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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trans_pcie->cmd_queue = trans_cfg->cmd_queue;
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trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
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if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
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trans_pcie->n_no_reclaim_cmds = 0;
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else
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@ -1536,17 +1533,6 @@ static void iwl_trans_pcie_configure(struct iwl_trans *trans,
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memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
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trans_pcie->n_no_reclaim_cmds * sizeof(u8));
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trans_pcie->n_q_to_fifo = trans_cfg->n_queue_to_fifo;
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if (WARN_ON(trans_pcie->n_q_to_fifo > IWL_MAX_HW_QUEUES))
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trans_pcie->n_q_to_fifo = IWL_MAX_HW_QUEUES;
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/* at least the command queue must be mapped */
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WARN_ON(!trans_pcie->n_q_to_fifo);
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memcpy(trans_pcie->setup_q_to_fifo, trans_cfg->queue_to_fifo,
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trans_pcie->n_q_to_fifo * sizeof(u8));
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trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
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if (trans_pcie->rx_buf_size_8k)
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trans_pcie->rx_page_order = get_order(8 * 1024);
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