mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 02:56:40 +07:00
powerpc: remove Wind River SBC8560 support
This reference board dates back to 2004, and is largely a legacy EOL product. The MPC8560 is a pre e500v2 CPU. The SBC8548 is a more modern, better e500v2 target for people to use as a reference board with today's kernels, should they require one. Removing support for it will also allow us to remove some sbc8560 specific quirk handling in 8250 UART code, and some MTD mapping support. Cc: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Paul Gortmaker
Kumar Gala
parent
572546b334
commit
b048b4e17c
@ -276,7 +276,6 @@ image-$(CONFIG_TQM8548) += cuImage.tqm8548
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image-$(CONFIG_TQM8555) += cuImage.tqm8555
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image-$(CONFIG_TQM8560) += cuImage.tqm8560
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image-$(CONFIG_SBC8548) += cuImage.sbc8548
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image-$(CONFIG_SBC8560) += cuImage.sbc8560
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image-$(CONFIG_KSI8560) += cuImage.ksi8560
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# Board ports in arch/powerpc/platform/embedded6xx/Kconfig
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@ -1,406 +0,0 @@
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/*
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* SBC8560 Device Tree Source
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*
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* Copyright 2007 Wind River Systems Inc.
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*
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* Paul Gortmaker (see MAINTAINERS for contact information)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "SBC8560";
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compatible = "SBC8560";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8560@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <0x20>; // 32 bytes
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i-cache-line-size = <0x20>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>; // From uboot
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bus-frequency = <0>;
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clock-frequency = <0>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x20000000>;
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};
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soc@ff700000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0x0 0xff700000 0x00100000>;
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clock-frequency = <0>;
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <8>;
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};
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ecm@1000 {
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compatible = "fsl,mpc8560-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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compatible = "fsl,mpc8560-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <0x12 0x2>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,mpc8560-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <0x20>; // 32 bytes
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cache-size = <0x40000>; // L2, 256K
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interrupt-parent = <&mpic>;
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interrupts = <0x10 0x2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <0x2b 0x2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <0x2b 0x2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8560-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8560-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8560-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8560-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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ranges = <0x0 0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy0: ethernet-phy@19 {
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interrupt-parent = <&mpic>;
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interrupts = <0x6 0x1>;
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reg = <0x19>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1a {
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interrupt-parent = <&mpic>;
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interrupts = <0x7 0x1>;
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reg = <0x1a>;
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device_type = "ethernet-phy";
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};
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phy2: ethernet-phy@1b {
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interrupt-parent = <&mpic>;
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interrupts = <0x8 0x1>;
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reg = <0x1b>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@1c {
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interrupt-parent = <&mpic>;
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interrupts = <0x8 0x1>;
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reg = <0x1c>;
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device_type = "ethernet-phy";
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet1: ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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ranges = <0x0 0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "chrp,open-pic";
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reg = <0x40000 0x40000>;
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device_type = "open-pic";
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};
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cpm@919c0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
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reg = <0x919c0 0x30>;
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ranges;
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muram@80000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x80000 0x10000>;
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data@0 {
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compatible = "fsl,cpm-muram-data";
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reg = <0x0 0x4000 0x9000 0x2000>;
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};
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};
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brg@919f0 {
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compatible = "fsl,mpc8560-brg",
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"fsl,cpm2-brg",
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"fsl,cpm-brg";
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reg = <0x919f0 0x10 0x915f0 0x10>;
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clock-frequency = <165000000>;
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};
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cpmpic: pic@90c00 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x2e 0x2>;
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interrupt-parent = <&mpic>;
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reg = <0x90c00 0x80>;
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compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
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};
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enet2: ethernet@91320 {
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device_type = "network";
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compatible = "fsl,mpc8560-fcc-enet",
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"fsl,cpm2-fcc-enet";
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reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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fsl,cpm-command = <0x16200300>;
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interrupts = <0x21 0x8>;
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interrupt-parent = <&cpmpic>;
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phy-handle = <&phy2>;
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};
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enet3: ethernet@91340 {
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device_type = "network";
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compatible = "fsl,mpc8560-fcc-enet",
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"fsl,cpm2-fcc-enet";
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reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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fsl,cpm-command = <0x1a400300>;
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interrupts = <0x22 0x8>;
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interrupt-parent = <&cpmpic>;
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phy-handle = <&phy3>;
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};
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};
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global-utilities@e0000 {
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compatible = "fsl,mpc8560-guts";
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reg = <0xe0000 0x1000>;
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};
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};
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pci0: pci@ff708000 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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reg = <0xff708000 0x1000>;
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clock-frequency = <66666666>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x02 */
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0x1000 0x0 0x0 0x1 &mpic 0x2 0x1
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0x1000 0x0 0x0 0x2 &mpic 0x3 0x1
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0x1000 0x0 0x0 0x3 &mpic 0x4 0x1
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0x1000 0x0 0x0 0x4 &mpic 0x5 0x1>;
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interrupt-parent = <&mpic>;
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interrupts = <0x18 0x2>;
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bus-range = <0x0 0x0>;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
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0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
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};
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localbus@ff705000 {
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compatible = "fsl,mpc8560-localbus", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0xff705000 0x100>; // BRx, ORx, etc.
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ranges = <
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0x0 0x0 0xff800000 0x0800000 // 8MB boot flash
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0x1 0x0 0xe4000000 0x4000000 // 64MB flash
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0x3 0x0 0x20000000 0x4000000 // 64MB SDRAM
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0x4 0x0 0x24000000 0x4000000 // 64MB SDRAM
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0x5 0x0 0xfc000000 0x0c00000 // EPLD
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0x6 0x0 0xe0000000 0x4000000 // 64MB flash
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0x7 0x0 0x80000000 0x0200000 // ATM1,2
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>;
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epld@5,0 {
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compatible = "wrs,epld-localbus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0x5 0x0 0xc00000>;
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ranges = <
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0x0 0x0 0x5 0x000000 0x1fff // LED disp.
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0x1 0x0 0x5 0x100000 0x1fff // switches
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0x2 0x0 0x5 0x200000 0x1fff // ID reg.
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0x3 0x0 0x5 0x300000 0x1fff // status reg.
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0x4 0x0 0x5 0x400000 0x1fff // reset reg.
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0x5 0x0 0x5 0x500000 0x1fff // Wind port
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0x7 0x0 0x5 0x700000 0x1fff // UART #1
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0x8 0x0 0x5 0x800000 0x1fff // UART #2
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0x9 0x0 0x5 0x900000 0x1fff // RTC
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0xb 0x0 0x5 0xb00000 0x1fff // EEPROM
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>;
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bidr@2,0 {
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compatible = "wrs,sbc8560-bidr";
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reg = <0x2 0x0 0x10>;
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};
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bcsr@3,0 {
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compatible = "wrs,sbc8560-bcsr";
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reg = <0x3 0x0 0x10>;
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};
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brstcr@4,0 {
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compatible = "wrs,sbc8560-brstcr";
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reg = <0x4 0x0 0x10>;
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};
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serial0: serial@7,0 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x7 0x0 0x100>;
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clock-frequency = <1843200>;
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interrupts = <0x9 0x2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@8,0 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x8 0x0 0x100>;
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clock-frequency = <1843200>;
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interrupts = <0xa 0x2>;
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interrupt-parent = <&mpic>;
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};
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rtc@9,0 {
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compatible = "m48t59";
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reg = <0x9 0x0 0x1fff>;
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};
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};
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};
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};
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@ -1,65 +0,0 @@
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CONFIG_PPC_85xx=y
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CONFIG_EXPERIMENTAL=y
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CONFIG_SYSVIPC=y
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CONFIG_LOG_BUF_SHIFT=14
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CONFIG_BLK_DEV_INITRD=y
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# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
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CONFIG_EXPERT=y
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CONFIG_SLAB=y
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_SBC8560=y
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CONFIG_BINFMT_MISC=y
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CONFIG_SPARSE_IRQ=y
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# CONFIG_SECCOMP is not set
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_XFRM_USER=y
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CONFIG_INET=y
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CONFIG_IP_MULTICAST=y
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CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
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CONFIG_IP_PNP_BOOTP=y
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CONFIG_SYN_COOKIES=y
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# CONFIG_INET_LRO is not set
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# CONFIG_IPV6 is not set
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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# CONFIG_FW_LOADER is not set
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CONFIG_PROC_DEVICETREE=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_RAM=y
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CONFIG_BLK_DEV_RAM_SIZE=32768
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CONFIG_NETDEVICES=y
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CONFIG_BROADCOM_PHY=y
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CONFIG_NET_ETHERNET=y
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CONFIG_MII=y
|
||||
CONFIG_GIANFAR=y
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_VIDEO_OUTPUT_CONTROL=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_M48T59=y
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_MSDOS_PARTITION is not set
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_PPC_EARLY_DEBUG=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
@ -175,12 +175,6 @@ config SBC8548
|
||||
help
|
||||
This option enables support for the Wind River SBC8548 board
|
||||
|
||||
config SBC8560
|
||||
bool "Wind River SBC8560"
|
||||
select DEFAULT_UIMAGE
|
||||
help
|
||||
This option enables support for the Wind River SBC8560 board
|
||||
|
||||
config GE_IMP3A
|
||||
bool "GE Intelligent Platforms IMP3A"
|
||||
select DEFAULT_UIMAGE
|
||||
|
||||
@ -22,7 +22,6 @@ obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
|
||||
obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
|
||||
obj-$(CONFIG_STX_GP3) += stx_gp3.o
|
||||
obj-$(CONFIG_TQM85xx) += tqm85xx.o
|
||||
obj-$(CONFIG_SBC8560) += sbc8560.o
|
||||
obj-$(CONFIG_SBC8548) += sbc8548.o
|
||||
obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
|
||||
obj-$(CONFIG_KSI8560) += ksi8560.o
|
||||
|
||||
@ -1,254 +0,0 @@
|
||||
/*
|
||||
* Wind River SBC8560 setup and early boot code.
|
||||
*
|
||||
* Copyright 2007 Wind River Systems Inc.
|
||||
*
|
||||
* By Paul Gortmaker (see MAINTAINERS for contact information)
|
||||
*
|
||||
* Based largely on the MPC8560ADS support - Copyright 2005 Freescale Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/mpic.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/udbg.h>
|
||||
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
|
||||
#include "mpc85xx.h"
|
||||
|
||||
#ifdef CONFIG_CPM2
|
||||
#include <asm/cpm2.h>
|
||||
#include <sysdev/cpm2_pic.h>
|
||||
#endif
|
||||
|
||||
static void __init sbc8560_pic_init(void)
|
||||
{
|
||||
struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
|
||||
0, 256, " OpenPIC ");
|
||||
BUG_ON(mpic == NULL);
|
||||
mpic_init(mpic);
|
||||
|
||||
mpc85xx_cpm2_pic_init();
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup the architecture
|
||||
*/
|
||||
#ifdef CONFIG_CPM2
|
||||
struct cpm_pin {
|
||||
int port, pin, flags;
|
||||
};
|
||||
|
||||
static const struct cpm_pin sbc8560_pins[] = {
|
||||
/* SCC1 */
|
||||
{3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
|
||||
{3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
|
||||
/* SCC2 */
|
||||
{3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
|
||||
/* FCC2 */
|
||||
{1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
|
||||
{1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
|
||||
{2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
|
||||
|
||||
/* FCC3 */
|
||||
{1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 7, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
|
||||
{1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
|
||||
{2, 16, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK16 */
|
||||
{2, 17, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK15 */
|
||||
};
|
||||
|
||||
static void __init init_ioports(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(sbc8560_pins); i++) {
|
||||
const struct cpm_pin *pin = &sbc8560_pins[i];
|
||||
cpm2_set_pin(pin->port, pin->pin, pin->flags);
|
||||
}
|
||||
|
||||
cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
|
||||
cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
|
||||
cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
|
||||
cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
|
||||
cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
|
||||
cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
|
||||
cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
|
||||
cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void __init sbc8560_setup_arch(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
struct device_node *np;
|
||||
#endif
|
||||
|
||||
if (ppc_md.progress)
|
||||
ppc_md.progress("sbc8560_setup_arch()", 0);
|
||||
|
||||
#ifdef CONFIG_CPM2
|
||||
cpm2_reset();
|
||||
init_ioports();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
|
||||
fsl_add_bridge(np, 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void sbc8560_show_cpuinfo(struct seq_file *m)
|
||||
{
|
||||
uint pvid, svid, phid1;
|
||||
|
||||
pvid = mfspr(SPRN_PVR);
|
||||
svid = mfspr(SPRN_SVR);
|
||||
|
||||
seq_printf(m, "Vendor\t\t: Wind River\n");
|
||||
seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
|
||||
seq_printf(m, "SVR\t\t: 0x%x\n", svid);
|
||||
|
||||
/* Display cpu Pll setting */
|
||||
phid1 = mfspr(SPRN_HID1);
|
||||
seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
|
||||
}
|
||||
|
||||
machine_device_initcall(sbc8560, mpc85xx_common_publish_devices);
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init sbc8560_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
return of_flat_dt_is_compatible(root, "SBC8560");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RTC_DRV_M48T59
|
||||
static int __init sbc8560_rtc_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct resource res;
|
||||
struct platform_device *rtc_dev;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "m48t59");
|
||||
if (np == NULL) {
|
||||
printk("No RTC in DTB. Has it been eaten by wild dogs?\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
of_address_to_resource(np, 0, &res);
|
||||
of_node_put(np);
|
||||
|
||||
printk("Found RTC (m48t59) at i/o 0x%x\n", res.start);
|
||||
|
||||
rtc_dev = platform_device_register_simple("rtc-m48t59", 0, &res, 1);
|
||||
|
||||
if (IS_ERR(rtc_dev)) {
|
||||
printk("Registering sbc8560 RTC device failed\n");
|
||||
return PTR_ERR(rtc_dev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(sbc8560_rtc_init);
|
||||
|
||||
#endif /* M48T59 */
|
||||
|
||||
static __u8 __iomem *brstcr;
|
||||
|
||||
static int __init sbc8560_bdrstcr_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct resource res;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "wrs,sbc8560-brstcr");
|
||||
if (np == NULL) {
|
||||
printk(KERN_WARNING "sbc8560: No board specific RSTCR in DTB.\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
of_address_to_resource(np, 0, &res);
|
||||
|
||||
printk(KERN_INFO "sbc8560: Found BRSTCR at %pR\n", &res);
|
||||
|
||||
brstcr = ioremap(res.start, resource_size(&res));
|
||||
if(!brstcr)
|
||||
printk(KERN_WARNING "sbc8560: ioremap of brstcr failed.\n");
|
||||
|
||||
of_node_put(np);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(sbc8560_bdrstcr_init);
|
||||
|
||||
void sbc8560_rstcr_restart(char * cmd)
|
||||
{
|
||||
local_irq_disable();
|
||||
if(brstcr)
|
||||
clrbits8(brstcr, 0x80);
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
define_machine(sbc8560) {
|
||||
.name = "SBC8560",
|
||||
.probe = sbc8560_probe,
|
||||
.setup_arch = sbc8560_setup_arch,
|
||||
.init_IRQ = sbc8560_pic_init,
|
||||
.show_cpuinfo = sbc8560_show_cpuinfo,
|
||||
.get_irq = mpic_get_irq,
|
||||
.restart = sbc8560_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user