mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 20:16:02 +07:00
drm/i915/gen11: Handle watermarks correctly for separate Y/UV planes, v2.
Skylake style watermarks program the UV parameters into wm->uv_wm, and have a separate DDB allocation for UV blocks into the same plane. Gen11 watermarks have a separate plane for Y and UV, with separate mechanisms. The simplest way to make it work is to keep the current way of programming watermarks and calculate the Y and UV plane watermarks from the master plane. Changes since v1: - Constify crtc_state where possible. - Make separate paths for planar formats in skl_build_pipe_wm() (Matt) - Make separate paths for calculating total data rate. (Matt) - Make sure UV watermarks are unused on gen11+ by adding a WARN. (Matt) Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181018115134.9061-5-maarten.lankhorst@linux.intel.com
This commit is contained in:
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1ab554b009
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@ -3814,7 +3814,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
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}
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static void
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skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
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skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
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const struct intel_crtc_state *cstate,
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const u64 total_data_rate,
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struct skl_ddb_allocation *ddb,
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@ -3823,7 +3823,6 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
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{
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struct drm_atomic_state *state = cstate->base.state;
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struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_crtc *for_crtc = cstate->base.crtc;
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const struct drm_crtc_state *crtc_state;
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const struct drm_crtc *crtc;
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@ -3945,14 +3944,9 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
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val & PLANE_CTL_ALPHA_MASK);
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val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
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/*
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* FIXME: add proper NV12 support for ICL. Avoid reading unclaimed
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* registers for now.
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*/
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if (INTEL_GEN(dev_priv) < 11)
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if (fourcc == DRM_FORMAT_NV12 && INTEL_GEN(dev_priv) < 11) {
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val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
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if (fourcc == DRM_FORMAT_NV12) {
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skl_ddb_entry_init_from_hw(dev_priv,
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&ddb->plane[pipe][plane_id], val2);
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skl_ddb_entry_init_from_hw(dev_priv,
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@ -4141,11 +4135,11 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
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static u64
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skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
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const struct drm_plane_state *pstate,
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const struct intel_plane_state *intel_pstate,
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const int plane)
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{
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struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
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struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
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struct intel_plane *intel_plane =
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to_intel_plane(intel_pstate->base.plane);
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uint32_t data_rate;
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uint32_t width = 0, height = 0;
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struct drm_framebuffer *fb;
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@ -4156,7 +4150,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
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if (!intel_pstate->base.visible)
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return 0;
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fb = pstate->fb;
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fb = intel_pstate->base.fb;
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format = fb->format->format;
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if (intel_plane->id == PLANE_CURSOR)
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@ -4206,25 +4200,80 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
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drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
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enum plane_id plane_id = to_intel_plane(plane)->id;
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u64 rate;
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const struct intel_plane_state *intel_pstate =
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to_intel_plane_state(pstate);
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/* packed/y */
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rate = skl_plane_relative_data_rate(intel_cstate,
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pstate, 0);
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intel_pstate, 0);
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plane_data_rate[plane_id] = rate;
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total_data_rate += rate;
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/* uv-plane */
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rate = skl_plane_relative_data_rate(intel_cstate,
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pstate, 1);
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intel_pstate, 1);
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uv_plane_data_rate[plane_id] = rate;
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total_data_rate += rate;
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}
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return total_data_rate;
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}
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static u64
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icl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
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u64 *plane_data_rate)
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{
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struct drm_crtc_state *cstate = &intel_cstate->base;
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struct drm_atomic_state *state = cstate->state;
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struct drm_plane *plane;
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const struct drm_plane_state *pstate;
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u64 total_data_rate = 0;
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if (WARN_ON(!state))
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return 0;
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/* Calculate and cache data rate for each plane */
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drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
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const struct intel_plane_state *intel_pstate =
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to_intel_plane_state(pstate);
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enum plane_id plane_id = to_intel_plane(plane)->id;
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u64 rate;
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if (!intel_pstate->linked_plane) {
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rate = skl_plane_relative_data_rate(intel_cstate,
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intel_pstate, 0);
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plane_data_rate[plane_id] = rate;
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total_data_rate += rate;
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} else {
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enum plane_id y_plane_id;
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/*
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* The slave plane might not iterate in
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* drm_atomic_crtc_state_for_each_plane_state(),
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* and needs the master plane state which may be
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* NULL if we try get_new_plane_state(), so we
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* always calculate from the master.
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*/
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if (intel_pstate->slave)
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continue;
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/* Y plane rate is calculated on the slave */
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rate = skl_plane_relative_data_rate(intel_cstate,
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intel_pstate, 0);
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y_plane_id = intel_pstate->linked_plane->id;
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plane_data_rate[y_plane_id] = rate;
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total_data_rate += rate;
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rate = skl_plane_relative_data_rate(intel_cstate,
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intel_pstate, 1);
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plane_data_rate[plane_id] = rate;
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total_data_rate += rate;
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}
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}
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return total_data_rate;
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}
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static uint16_t
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skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
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{
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@ -4297,15 +4346,25 @@ skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
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drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
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enum plane_id plane_id = to_intel_plane(plane)->id;
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struct intel_plane_state *plane_state = to_intel_plane_state(pstate);
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if (plane_id == PLANE_CURSOR)
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continue;
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if (!pstate->visible)
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/* slave plane must be invisible and calculated from master */
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if (!pstate->visible || WARN_ON(plane_state->slave))
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continue;
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minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
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uv_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
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if (!plane_state->linked_plane) {
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minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
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uv_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
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} else {
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enum plane_id y_plane_id =
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plane_state->linked_plane->id;
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minimum[y_plane_id] = skl_ddb_min_alloc(pstate, 0);
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minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
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}
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}
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minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
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@ -4317,7 +4376,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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{
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struct drm_atomic_state *state = cstate->base.state;
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struct drm_crtc *crtc = cstate->base.crtc;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(crtc->dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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enum pipe pipe = intel_crtc->pipe;
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struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
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@ -4343,11 +4402,18 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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return 0;
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}
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total_data_rate = skl_get_total_relative_data_rate(cstate,
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plane_data_rate,
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uv_plane_data_rate);
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skl_ddb_get_pipe_allocation_limits(dev, cstate, total_data_rate, ddb,
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alloc, &num_active);
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if (INTEL_GEN(dev_priv) < 11)
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total_data_rate =
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skl_get_total_relative_data_rate(cstate,
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plane_data_rate,
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uv_plane_data_rate);
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else
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total_data_rate =
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icl_get_total_relative_data_rate(cstate,
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plane_data_rate);
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skl_ddb_get_pipe_allocation_limits(dev_priv, cstate, total_data_rate,
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ddb, alloc, &num_active);
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alloc_size = skl_ddb_entry_size(alloc);
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if (alloc_size == 0)
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return 0;
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@ -4417,6 +4483,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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uv_plane_blocks = uv_minimum[plane_id];
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uv_plane_blocks += div64_u64(alloc_size * uv_data_rate, total_data_rate);
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/* Gen11+ uses a separate plane for UV watermarks */
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WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_plane_blocks);
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if (uv_data_rate) {
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ddb->uv_plane[pipe][plane_id].start = start;
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ddb->uv_plane[pipe][plane_id].end =
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@ -4473,7 +4542,7 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
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}
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static uint_fixed_16_16_t
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intel_get_linetime_us(struct intel_crtc_state *cstate)
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intel_get_linetime_us(const struct intel_crtc_state *cstate)
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{
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uint32_t pixel_rate;
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uint32_t crtc_htotal;
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@ -4517,7 +4586,7 @@ skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
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static int
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skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
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struct intel_crtc_state *cstate,
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const struct intel_crtc_state *cstate,
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const struct intel_plane_state *intel_pstate,
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struct skl_wm_params *wp, int plane_id)
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{
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@ -4624,7 +4693,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
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}
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static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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struct intel_crtc_state *cstate,
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const struct intel_crtc_state *cstate,
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const struct intel_plane_state *intel_pstate,
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uint16_t ddb_allocation,
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int level,
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@ -4784,38 +4853,22 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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static int
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skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
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struct skl_ddb_allocation *ddb,
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struct intel_crtc_state *cstate,
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const struct intel_crtc_state *cstate,
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const struct intel_plane_state *intel_pstate,
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uint16_t ddb_blocks,
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const struct skl_wm_params *wm_params,
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struct skl_plane_wm *wm,
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int plane_id)
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struct skl_wm_level *levels)
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{
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struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
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struct drm_plane *plane = intel_pstate->base.plane;
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struct intel_plane *intel_plane = to_intel_plane(plane);
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uint16_t ddb_blocks;
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enum pipe pipe = intel_crtc->pipe;
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int level, max_level = ilk_wm_max_level(dev_priv);
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enum plane_id intel_plane_id = intel_plane->id;
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struct skl_wm_level *result_prev = &levels[0];
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int ret;
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if (WARN_ON(!intel_pstate->base.fb))
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return -EINVAL;
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ddb_blocks = plane_id ?
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skl_ddb_entry_size(&ddb->uv_plane[pipe][intel_plane_id]) :
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skl_ddb_entry_size(&ddb->plane[pipe][intel_plane_id]);
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for (level = 0; level <= max_level; level++) {
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struct skl_wm_level *result = plane_id ? &wm->uv_wm[level] :
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&wm->wm[level];
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struct skl_wm_level *result_prev;
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if (level)
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result_prev = plane_id ? &wm->uv_wm[level - 1] :
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&wm->wm[level - 1];
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else
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result_prev = plane_id ? &wm->uv_wm[0] : &wm->wm[0];
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struct skl_wm_level *result = &levels[level];
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ret = skl_compute_plane_wm(dev_priv,
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cstate,
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@ -4827,6 +4880,8 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
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result);
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if (ret)
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return ret;
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result_prev = result;
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}
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if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
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@ -4836,7 +4891,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
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}
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static uint32_t
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skl_compute_linetime_wm(struct intel_crtc_state *cstate)
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skl_compute_linetime_wm(const struct intel_crtc_state *cstate)
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{
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struct drm_atomic_state *state = cstate->base.state;
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struct drm_i915_private *dev_priv = to_i915(state->dev);
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@ -4858,7 +4913,7 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate)
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return linetime_wm;
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}
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static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
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static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
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struct skl_wm_params *wp,
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struct skl_wm_level *wm_l0,
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uint16_t ddb_allocation,
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@ -4925,16 +4980,101 @@ static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
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trans_wm->plane_en = false;
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}
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static int __skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
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struct skl_pipe_wm *pipe_wm,
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enum plane_id plane_id,
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const struct intel_crtc_state *cstate,
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const struct intel_plane_state *pstate,
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int color_plane)
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{
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struct drm_i915_private *dev_priv = to_i915(pstate->base.plane->dev);
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struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
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enum pipe pipe = to_intel_plane(pstate->base.plane)->pipe;
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struct skl_wm_params wm_params;
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uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
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int ret;
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ret = skl_compute_plane_wm_params(dev_priv, cstate, pstate,
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&wm_params, color_plane);
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if (ret)
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return ret;
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ret = skl_compute_wm_levels(dev_priv, ddb, cstate, pstate,
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ddb_blocks, &wm_params, wm, wm->wm);
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if (ret)
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return ret;
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skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
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ddb_blocks, &wm->trans_wm);
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return 0;
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}
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static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
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struct skl_pipe_wm *pipe_wm,
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const struct intel_crtc_state *cstate,
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const struct intel_plane_state *pstate)
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{
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enum plane_id plane_id = to_intel_plane(pstate->base.plane)->id;
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return __skl_build_plane_wm_single(ddb, pipe_wm, plane_id, cstate, pstate, 0);
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}
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static int skl_build_plane_wm_planar(struct skl_ddb_allocation *ddb,
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struct skl_pipe_wm *pipe_wm,
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const struct intel_crtc_state *cstate,
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const struct intel_plane_state *pstate)
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{
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struct intel_plane *plane = to_intel_plane(pstate->base.plane);
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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enum plane_id plane_id = plane->id;
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struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
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struct skl_wm_params wm_params;
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enum pipe pipe = plane->pipe;
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uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
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int ret;
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ret = __skl_build_plane_wm_single(ddb, pipe_wm, plane_id, cstate, pstate, 0);
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if (ret)
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return ret;
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/* uv plane watermarks must also be validated for NV12/Planar */
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ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
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ret = skl_compute_plane_wm_params(dev_priv, cstate, pstate, &wm_params, 1);
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if (ret)
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return ret;
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return skl_compute_wm_levels(dev_priv, ddb, cstate, pstate,
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ddb_blocks, &wm_params, wm, wm->uv_wm);
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}
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static int icl_build_plane_wm_planar(struct skl_ddb_allocation *ddb,
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struct skl_pipe_wm *pipe_wm,
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const struct intel_crtc_state *cstate,
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const struct intel_plane_state *pstate)
|
||||
{
|
||||
int ret;
|
||||
enum plane_id y_plane_id = pstate->linked_plane->id;
|
||||
enum plane_id uv_plane_id = to_intel_plane(pstate->base.plane)->id;
|
||||
|
||||
ret = __skl_build_plane_wm_single(ddb, pipe_wm, y_plane_id,
|
||||
cstate, pstate, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return __skl_build_plane_wm_single(ddb, pipe_wm, uv_plane_id,
|
||||
cstate, pstate, 1);
|
||||
}
|
||||
|
||||
static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
|
||||
struct skl_ddb_allocation *ddb,
|
||||
struct skl_pipe_wm *pipe_wm)
|
||||
{
|
||||
struct drm_device *dev = cstate->base.crtc->dev;
|
||||
struct drm_crtc_state *crtc_state = &cstate->base;
|
||||
const struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
struct drm_plane *plane;
|
||||
const struct drm_plane_state *pstate;
|
||||
struct skl_plane_wm *wm;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
@ -4946,44 +5086,21 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
|
||||
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
|
||||
const struct intel_plane_state *intel_pstate =
|
||||
to_intel_plane_state(pstate);
|
||||
enum plane_id plane_id = to_intel_plane(plane)->id;
|
||||
struct skl_wm_params wm_params;
|
||||
enum pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe;
|
||||
uint16_t ddb_blocks;
|
||||
|
||||
wm = &pipe_wm->planes[plane_id];
|
||||
ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
|
||||
/* Watermarks calculated in master */
|
||||
if (intel_pstate->slave)
|
||||
continue;
|
||||
|
||||
if (intel_pstate->linked_plane)
|
||||
ret = icl_build_plane_wm_planar(ddb, pipe_wm, cstate, intel_pstate);
|
||||
else if (intel_pstate->base.fb &&
|
||||
intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
|
||||
ret = skl_build_plane_wm_planar(ddb, pipe_wm, cstate, intel_pstate);
|
||||
else
|
||||
ret = skl_build_plane_wm_single(ddb, pipe_wm, cstate, intel_pstate);
|
||||
|
||||
ret = skl_compute_plane_wm_params(dev_priv, cstate,
|
||||
intel_pstate, &wm_params, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
|
||||
intel_pstate, &wm_params, wm, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
|
||||
ddb_blocks, &wm->trans_wm);
|
||||
|
||||
/* uv plane watermarks must also be validated for NV12/Planar */
|
||||
if (wm_params.is_planar) {
|
||||
memset(&wm_params, 0, sizeof(struct skl_wm_params));
|
||||
wm->is_planar = true;
|
||||
|
||||
ret = skl_compute_plane_wm_params(dev_priv, cstate,
|
||||
intel_pstate,
|
||||
&wm_params, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
|
||||
intel_pstate, &wm_params,
|
||||
wm, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
pipe_wm->linetime = skl_compute_linetime_wm(cstate);
|
||||
@ -5034,12 +5151,7 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
|
||||
skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
|
||||
&wm->trans_wm);
|
||||
|
||||
/* FIXME: add proper NV12 support for ICL. */
|
||||
if (INTEL_GEN(dev_priv) >= 11)
|
||||
return skl_ddb_entry_write(dev_priv,
|
||||
PLANE_BUF_CFG(pipe, plane_id),
|
||||
&ddb->plane[pipe][plane_id]);
|
||||
if (wm->is_planar) {
|
||||
if (wm->is_planar && INTEL_GEN(dev_priv) < 11) {
|
||||
skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
|
||||
&ddb->uv_plane[pipe][plane_id]);
|
||||
skl_ddb_entry_write(dev_priv,
|
||||
@ -5048,7 +5160,8 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
|
||||
} else {
|
||||
skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
|
||||
&ddb->plane[pipe][plane_id]);
|
||||
I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);
|
||||
if (INTEL_GEN(dev_priv) < 11)
|
||||
I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);
|
||||
}
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user