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ath9k: Differentiate between max combined and per chain power
The ath9k driver uses as maximum allowed txpower the constant MAX_RATE_POWER. It is used to set a maximum txpower limit for the PHY (which is combined txpower) and also the maximum txpower for per chain rates. Its value 63 is derived from the maximum number the registers can store for the per chain txpower. The max txpower a user can set because of this is 31 dBm (floor(63 / 2)). This also means that a device with multiple tx chains is even limited further: * 1 chain: 31 dBm per chain * 2 chains: 28 dBm per chain * 3 chains: 26 dBm per chain This combined txpower limit of 31 dBm becomes even more problematic when some extra antenna gain is set in the EEPROM. A high power device is then no longer able to reach its potential limits. Instead the code dealing with the combined txpower must use a higher limit than 63 and only the code dealing with the per chain txpower have to use the limit of 63. Since the antenna gain can be quite large and 8 bit variables are often used in ath9k for txpower, a large, divisible by two number like 254 is a good choice for this new limit. Signed-off-by: Sven Eckelmann <sven@narfation.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -428,7 +428,7 @@ u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit,
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else
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power_limit = 0;
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return power_limit;
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return min_t(u16, power_limit, MAX_RATE_POWER);
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}
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void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
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@ -424,6 +424,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
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ath9k_hw_get_channel_centers(ah, chan, ¢ers);
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scaledPower = powerLimit - antenna_reduction;
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scaledPower = min_t(u16, scaledPower, MAX_RATE_POWER);
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numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
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pCtlMode = ctlModesFor11g;
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@ -457,7 +457,7 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
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struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
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regulatory->country_code = CTRY_DEFAULT;
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regulatory->power_limit = MAX_RATE_POWER;
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regulatory->power_limit = MAX_COMBINED_POWER;
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ah->hw_version.magic = AR5416_MAGIC;
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ah->hw_version.subvendorid = 0;
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@ -2966,7 +2966,7 @@ void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
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ctl = ath9k_regd_get_ctl(reg, chan);
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channel = chan->chan;
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chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
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chan_pwr = min_t(int, channel->max_power * 2, MAX_COMBINED_POWER);
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new_pwr = min_t(int, chan_pwr, reg->power_limit);
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ah->eep_ops->set_txpower(ah, chan, ctl,
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@ -2979,9 +2979,9 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
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struct ath9k_channel *chan = ah->curchan;
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struct ieee80211_channel *channel = chan->chan;
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reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
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reg->power_limit = min_t(u32, limit, MAX_COMBINED_POWER);
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if (test)
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channel->max_power = MAX_RATE_POWER / 2;
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channel->max_power = MAX_COMBINED_POWER / 2;
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ath9k_hw_apply_txpower(ah, chan, test);
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@ -173,6 +173,7 @@
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#define ATH9K_NUM_QUEUES 10
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#define MAX_RATE_POWER 63
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#define MAX_COMBINED_POWER 254 /* 128 dBm, chosen to fit in u8 */
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#define AH_WAIT_TIMEOUT 100000 /* (us) */
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#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
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#define AH_TIME_QUANTUM 10
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@ -805,7 +805,7 @@ static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
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ah->curchan = &ah->channels[chan->hw_value];
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cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
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ath9k_cmn_get_channel(sc->hw, ah, &chandef);
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ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
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ath9k_hw_set_txpowerlimit(ah, MAX_COMBINED_POWER, true);
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}
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}
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