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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 15:56:49 +07:00
b43: N-PHY: add helper for getting gain table
Also move the code to tables file. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Rafał Miłecki
John W. Linville
parent
d3fd8bf77a
commit
aeab57517c
@ -85,24 +85,6 @@ static inline bool b43_nphy_ipa(struct b43_wldev *dev)
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(dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
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}
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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
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static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
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{
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
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if (dev->phy.rev >= 6) {
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if (dev->dev->chip_id == 47162)
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return txpwrctrl_tx_gain_ipa_rev5;
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return txpwrctrl_tx_gain_ipa_rev6;
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} else if (dev->phy.rev >= 5) {
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return txpwrctrl_tx_gain_ipa_rev5;
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} else {
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return txpwrctrl_tx_gain_ipa;
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}
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} else {
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return txpwrctrl_tx_gain_ipa_5g;
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}
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}
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/**************************************************
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* RF (just without b43_nphy_rf_control_intc_override)
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**************************************************/
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@ -2229,27 +2211,12 @@ static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
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*/
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for (i = 0; i < 2; i++) {
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if (dev->phy.rev >= 3) {
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if (b43_nphy_ipa(dev)) {
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txgain = *(b43_nphy_get_ipa_gain_table(dev) +
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txpi[i]);
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} else if (b43_current_band(dev->wl) ==
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IEEE80211_BAND_5GHZ) {
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/* FIXME: use 5GHz tables */
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txgain =
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b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
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} else {
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if (dev->phy.rev >= 5 &&
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sprom->fem.ghz5.extpa_gain == 3)
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; /* FIXME: 5GHz_txgain_HiPwrEPA */
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txgain =
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b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
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}
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txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
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if (dev->phy.rev >= 3)
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radio_gain = (txgain >> 16) & 0x1FFFF;
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} else {
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txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
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else
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radio_gain = (txgain >> 16) & 0x1FFF;
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}
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if (dev->phy.rev >= 7)
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dac_gain = (txgain >> 8) & 0x7;
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@ -2647,24 +2614,7 @@ static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
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int i;
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#endif
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if (phy->rev >= 3) {
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if (b43_nphy_ipa(dev)) {
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table = b43_nphy_get_ipa_gain_table(dev);
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} else {
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if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
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if (phy->rev == 3)
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table = b43_ntab_tx_gain_rev3_5ghz;
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if (phy->rev == 4)
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table = b43_ntab_tx_gain_rev4_5ghz;
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else
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table = b43_ntab_tx_gain_rev5plus_5ghz;
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} else {
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table = b43_ntab_tx_gain_rev3plus_2ghz;
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}
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}
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} else {
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table = b43_ntab_tx_gain_rev0_1_2;
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}
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table = b43_nphy_get_tx_gain_table(dev);
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b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
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b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
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@ -3354,32 +3304,13 @@ static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
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B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
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for (i = 0; i < 2; ++i) {
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table = b43_nphy_get_tx_gain_table(dev);
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if (dev->phy.rev >= 3) {
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enum ieee80211_band band =
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b43_current_band(dev->wl);
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if (b43_nphy_ipa(dev)) {
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table = b43_nphy_get_ipa_gain_table(dev);
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} else {
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if (band == IEEE80211_BAND_5GHZ) {
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if (dev->phy.rev == 3)
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table = b43_ntab_tx_gain_rev3_5ghz;
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else if (dev->phy.rev == 4)
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table = b43_ntab_tx_gain_rev4_5ghz;
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else
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table = b43_ntab_tx_gain_rev5plus_5ghz;
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} else {
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table = b43_ntab_tx_gain_rev3plus_2ghz;
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}
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}
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target.ipa[i] = (table[index[i]] >> 16) & 0xF;
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target.pad[i] = (table[index[i]] >> 20) & 0xF;
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target.pga[i] = (table[index[i]] >> 24) & 0xF;
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target.txgm[i] = (table[index[i]] >> 28) & 0xF;
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} else {
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table = b43_ntab_tx_gain_rev0_1_2;
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target.ipa[i] = (table[index[i]] >> 16) & 0x3;
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target.pad[i] = (table[index[i]] >> 18) & 0x3;
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target.pga[i] = (table[index[i]] >> 20) & 0x7;
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@ -2214,7 +2214,7 @@ static const u16 b43_ntab_antswctl2g_r3[4][32] = {
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};
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/* TX gain tables */
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const u32 b43_ntab_tx_gain_rev0_1_2[] = {
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static const u32 b43_ntab_tx_gain_rev0_1_2[] = {
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0x03cc2b44, 0x03cc2b42, 0x03cc2a44, 0x03cc2a42,
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0x03cc2944, 0x03c82b44, 0x03c82b42, 0x03c82a44,
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0x03c82a42, 0x03c82944, 0x03c82942, 0x03c82844,
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@ -2249,7 +2249,7 @@ const u32 b43_ntab_tx_gain_rev0_1_2[] = {
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0x03801442, 0x03801344, 0x03801342, 0x00002b00,
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};
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const u32 b43_ntab_tx_gain_rev3plus_2ghz[] = {
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static const u32 b43_ntab_tx_gain_rev3plus_2ghz[] = {
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0x1f410044, 0x1f410042, 0x1f410040, 0x1f41003e,
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0x1f41003c, 0x1f41003b, 0x1f410039, 0x1f410037,
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0x1e410044, 0x1e410042, 0x1e410040, 0x1e41003e,
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@ -2284,7 +2284,7 @@ const u32 b43_ntab_tx_gain_rev3plus_2ghz[] = {
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0x1041003c, 0x1041003b, 0x10410039, 0x10410037,
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};
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const u32 b43_ntab_tx_gain_rev3_5ghz[] = {
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static const u32 b43_ntab_tx_gain_rev3_5ghz[] = {
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0xcff70044, 0xcff70042, 0xcff70040, 0xcff7003e,
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0xcff7003c, 0xcff7003b, 0xcff70039, 0xcff70037,
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0xcef70044, 0xcef70042, 0xcef70040, 0xcef7003e,
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@ -2319,7 +2319,7 @@ const u32 b43_ntab_tx_gain_rev3_5ghz[] = {
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0xc0f7003c, 0xc0f7003b, 0xc0f70039, 0xc0f70037,
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};
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const u32 b43_ntab_tx_gain_rev4_5ghz[] = {
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static const u32 b43_ntab_tx_gain_rev4_5ghz[] = {
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0x2ff20044, 0x2ff20042, 0x2ff20040, 0x2ff2003e,
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0x2ff2003c, 0x2ff2003b, 0x2ff20039, 0x2ff20037,
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0x2ef20044, 0x2ef20042, 0x2ef20040, 0x2ef2003e,
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@ -2354,7 +2354,7 @@ const u32 b43_ntab_tx_gain_rev4_5ghz[] = {
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0x20d2003a, 0x20d20038, 0x20d20036, 0x20d20034,
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};
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const u32 b43_ntab_tx_gain_rev5plus_5ghz[] = {
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static const u32 b43_ntab_tx_gain_rev5plus_5ghz[] = {
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0x0f62004a, 0x0f620048, 0x0f620046, 0x0f620044,
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0x0f620042, 0x0f620040, 0x0f62003e, 0x0f62003c,
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0x0e620044, 0x0e620042, 0x0e620040, 0x0e62003e,
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@ -2389,7 +2389,7 @@ const u32 b43_ntab_tx_gain_rev5plus_5ghz[] = {
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0x0062003b, 0x00620039, 0x00620037, 0x00620035,
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};
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const u32 txpwrctrl_tx_gain_ipa[] = {
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static const u32 txpwrctrl_tx_gain_ipa[] = {
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0x5ff7002d, 0x5ff7002b, 0x5ff7002a, 0x5ff70029,
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0x5ff70028, 0x5ff70027, 0x5ff70026, 0x5ff70025,
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0x5ef7002d, 0x5ef7002b, 0x5ef7002a, 0x5ef70029,
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@ -2424,7 +2424,7 @@ const u32 txpwrctrl_tx_gain_ipa[] = {
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0x50f70028, 0x50f70027, 0x50f70026, 0x50f70025,
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};
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const u32 txpwrctrl_tx_gain_ipa_rev5[] = {
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static const u32 txpwrctrl_tx_gain_ipa_rev5[] = {
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0x1ff7002d, 0x1ff7002b, 0x1ff7002a, 0x1ff70029,
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0x1ff70028, 0x1ff70027, 0x1ff70026, 0x1ff70025,
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0x1ef7002d, 0x1ef7002b, 0x1ef7002a, 0x1ef70029,
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@ -2459,7 +2459,7 @@ const u32 txpwrctrl_tx_gain_ipa_rev5[] = {
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0x10f70028, 0x10f70027, 0x10f70026, 0x10f70025,
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};
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const u32 txpwrctrl_tx_gain_ipa_rev6[] = {
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static const u32 txpwrctrl_tx_gain_ipa_rev6[] = {
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0x0ff7002d, 0x0ff7002b, 0x0ff7002a, 0x0ff70029,
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0x0ff70028, 0x0ff70027, 0x0ff70026, 0x0ff70025,
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0x0ef7002d, 0x0ef7002b, 0x0ef7002a, 0x0ef70029,
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@ -2494,7 +2494,7 @@ const u32 txpwrctrl_tx_gain_ipa_rev6[] = {
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0x00f70028, 0x00f70027, 0x00f70026, 0x00f70025,
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};
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const u32 txpwrctrl_tx_gain_ipa_5g[] = {
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static const u32 txpwrctrl_tx_gain_ipa_5g[] = {
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0x7ff70035, 0x7ff70033, 0x7ff70032, 0x7ff70031,
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0x7ff7002f, 0x7ff7002e, 0x7ff7002d, 0x7ff7002b,
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0x7ff7002a, 0x7ff70029, 0x7ff70028, 0x7ff70027,
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@ -3126,6 +3126,53 @@ void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev)
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B43_WARN_ON(1);
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}
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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
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static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
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{
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
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if (dev->phy.rev >= 6) {
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if (dev->dev->chip_id == 47162)
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return txpwrctrl_tx_gain_ipa_rev5;
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return txpwrctrl_tx_gain_ipa_rev6;
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} else if (dev->phy.rev >= 5) {
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return txpwrctrl_tx_gain_ipa_rev5;
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} else {
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return txpwrctrl_tx_gain_ipa;
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}
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} else {
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return txpwrctrl_tx_gain_ipa_5g;
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}
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}
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const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev)
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{
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enum ieee80211_band band = b43_current_band(dev->wl);
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struct ssb_sprom *sprom = dev->dev->bus_sprom;
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if (dev->phy.rev < 3)
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return b43_ntab_tx_gain_rev0_1_2;
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/* rev 3+ */
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if ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
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(dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ)) {
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return b43_nphy_get_ipa_gain_table(dev);
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} else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
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if (dev->phy.rev == 3)
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return b43_ntab_tx_gain_rev3_5ghz;
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if (dev->phy.rev == 4)
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return sprom->fem.ghz5.extpa_gain == 3 ?
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b43_ntab_tx_gain_rev4_5ghz :
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b43_ntab_tx_gain_rev4_5ghz; /* FIXME */
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else
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return b43_ntab_tx_gain_rev5plus_5ghz;
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} else {
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if (dev->phy.rev >= 5 && sprom->fem.ghz5.extpa_gain == 3)
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return b43_ntab_tx_gain_rev3plus_2ghz; /* FIXME */
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else
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return b43_ntab_tx_gain_rev3plus_2ghz;
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}
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}
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struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
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struct b43_wldev *dev, bool ghz5, bool ext_lna)
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{
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@ -177,16 +177,8 @@ void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
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void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev);
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void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev);
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extern const u32 b43_ntab_tx_gain_rev0_1_2[];
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extern const u32 b43_ntab_tx_gain_rev3plus_2ghz[];
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extern const u32 b43_ntab_tx_gain_rev3_5ghz[];
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extern const u32 b43_ntab_tx_gain_rev4_5ghz[];
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extern const u32 b43_ntab_tx_gain_rev5plus_5ghz[];
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const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev);
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extern const u32 txpwrctrl_tx_gain_ipa[];
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extern const u32 txpwrctrl_tx_gain_ipa_rev5[];
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extern const u32 txpwrctrl_tx_gain_ipa_rev6[];
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extern const u32 txpwrctrl_tx_gain_ipa_5g[];
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extern const u16 tbl_iqcal_gainparams[2][9][8];
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extern const struct nphy_txiqcal_ladder ladder_lo[];
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extern const struct nphy_txiqcal_ladder ladder_iq[];
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