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drm/i915: Fix CHV DSI PLL refclk during state readout
Use the proper refclock frequency (100MHz) when reading out the current DSI clock on CHV. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458052809-23426-13-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
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@ -258,7 +258,7 @@ static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
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u32 dsi_clock, pclk;
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u32 pll_ctl, pll_div;
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u32 m = 0, p = 0, n;
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int refclk = 25000;
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int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
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int i;
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DRM_DEBUG_KMS("\n");
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