mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 21:16:44 +07:00
Merge branch 'asoc-4.21' into HEAD
This commit is contained in:
commit
ae33ba2a8b
@ -1128,8 +1128,11 @@ static int rt274_i2c_probe(struct i2c_client *i2c,
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return ret;
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}
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regmap_read(rt274->regmap,
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ret = regmap_read(rt274->regmap,
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RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val);
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if (ret)
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return ret;
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if (val != RT274_VENDOR_ID) {
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dev_err(&i2c->dev,
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"Device with ID register %#x is not rt274\n", val);
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@ -108,7 +108,7 @@ struct davinci_mcasp {
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/* Used for comstraint setting on the second stream */
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u32 channels;
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#ifdef CONFIG_PM_SLEEP
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#ifdef CONFIG_PM
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struct davinci_mcasp_context context;
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#endif
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@ -1486,74 +1486,6 @@ static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
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{
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struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
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struct davinci_mcasp_context *context = &mcasp->context;
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u32 reg;
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int i;
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context->pm_state = pm_runtime_active(mcasp->dev);
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if (!context->pm_state)
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pm_runtime_get_sync(mcasp->dev);
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for (i = 0; i < ARRAY_SIZE(context_regs); i++)
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context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
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if (mcasp->txnumevt) {
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reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
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context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
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}
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if (mcasp->rxnumevt) {
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reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
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context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
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}
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for (i = 0; i < mcasp->num_serializer; i++)
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context->xrsr_regs[i] = mcasp_get_reg(mcasp,
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DAVINCI_MCASP_XRSRCTL_REG(i));
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pm_runtime_put_sync(mcasp->dev);
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return 0;
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}
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static int davinci_mcasp_resume(struct snd_soc_dai *dai)
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{
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struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
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struct davinci_mcasp_context *context = &mcasp->context;
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u32 reg;
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int i;
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pm_runtime_get_sync(mcasp->dev);
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for (i = 0; i < ARRAY_SIZE(context_regs); i++)
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mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
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if (mcasp->txnumevt) {
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reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
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mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
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}
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if (mcasp->rxnumevt) {
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reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
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mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
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}
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for (i = 0; i < mcasp->num_serializer; i++)
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mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
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context->xrsr_regs[i]);
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if (!context->pm_state)
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pm_runtime_put_sync(mcasp->dev);
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return 0;
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}
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#else
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#define davinci_mcasp_suspend NULL
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#define davinci_mcasp_resume NULL
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#endif
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#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
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#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
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@ -1571,8 +1503,6 @@ static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
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{
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.name = "davinci-mcasp.0",
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.probe = davinci_mcasp_dai_probe,
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.suspend = davinci_mcasp_suspend,
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.resume = davinci_mcasp_resume,
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.playback = {
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.channels_min = 1,
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.channels_max = 32 * 16,
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@ -1976,7 +1906,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
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}
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mcasp->num_serializer = pdata->num_serializer;
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#ifdef CONFIG_PM_SLEEP
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#ifdef CONFIG_PM
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mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
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mcasp->num_serializer, sizeof(u32),
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GFP_KERNEL);
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@ -2180,11 +2110,73 @@ static int davinci_mcasp_remove(struct platform_device *pdev)
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return 0;
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}
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#ifdef CONFIG_PM
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static int davinci_mcasp_runtime_suspend(struct device *dev)
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{
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struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
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struct davinci_mcasp_context *context = &mcasp->context;
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u32 reg;
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int i;
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for (i = 0; i < ARRAY_SIZE(context_regs); i++)
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context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
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if (mcasp->txnumevt) {
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reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
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context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
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}
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if (mcasp->rxnumevt) {
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reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
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context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
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}
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for (i = 0; i < mcasp->num_serializer; i++)
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context->xrsr_regs[i] = mcasp_get_reg(mcasp,
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DAVINCI_MCASP_XRSRCTL_REG(i));
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return 0;
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}
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static int davinci_mcasp_runtime_resume(struct device *dev)
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{
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struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
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struct davinci_mcasp_context *context = &mcasp->context;
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u32 reg;
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int i;
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for (i = 0; i < ARRAY_SIZE(context_regs); i++)
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mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
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if (mcasp->txnumevt) {
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reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
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mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
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}
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if (mcasp->rxnumevt) {
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reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
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mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
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}
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for (i = 0; i < mcasp->num_serializer; i++)
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mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
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context->xrsr_regs[i]);
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return 0;
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}
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#endif
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static const struct dev_pm_ops davinci_mcasp_pm_ops = {
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SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
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davinci_mcasp_runtime_resume,
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NULL)
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};
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static struct platform_driver davinci_mcasp_driver = {
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.probe = davinci_mcasp_probe,
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.remove = davinci_mcasp_remove,
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.driver = {
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.name = "davinci-mcasp",
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.pm = &davinci_mcasp_pm_ops,
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.of_match_table = mcasp_dt_ids,
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},
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};
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