AuxXxilium/linux_dsm_epyc7002
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Merge branch 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/renesas into next/soc

Browse Source 
* 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/renesas: (234 commits)
  ARM: shmobile: remove additional __io() macro use
  ARM: mach-shmobile: default to no earlytimer
  ARM: mach-shmobile: r8a7779 and Marzen timer rework
  ARM: mach-shmobile: r8a7740 and Bonito timer rework
  ARM: mach-shmobile: sh73a0, AG5EVM and Kota2 timer rework
  ARM: mach-shmobile: sh7372, AP4EVB and Mackerel timer rework
  ARM: mach-shmobile: sh7377 and G4EVM timer rework
  ARM: mach-shmobile: sh7367 and G3EVM timer rework
  ARM: mach-shmobile: add shmobile_earlytimer_init()
  ARM: mach-shmobile: Move sh7372 AP4EVB external clk setup
  ARM: mach-shmobile: Move sh7372 Mackerel external clk setup
  ARM: mach-shmobile: rename clk_init() to shmobile_clk_init()
  ARM: mach-shmobile: r8a7779 L2 cache support
  ARM: mach-shmobile: r8a7779 map_io and init_early update
  ARM: mach-shmobile: r8a7740 map_io and init_early update
  ARM: mach-shmobile: sh73a0 map_io and init_early update
  ARM: mach-shmobile: sh7372 map_io and init_early update
  ARM: mach-shmobile: sh7377 map_io and init_early update
  ARM: mach-shmobile: sh7367 map_io and init_early update
  sh: remove clk_ops
  ...

  (includes an update to v3.3-rc7)

Conflicts:
	arch/arm/mach-omap2/id.c
This commit is contained in:
Olof Johansson 2012-03-13 17:38:09 -07:00
commit ae0b82504e
274 changed files with 1656 additions and 1188 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/gpio/led.txt
View File

@ -7,9 +7,9 @@ Each LED is represented as a sub-node of the gpio-leds device. Each
node's name represents the name of the corresponding LED.
LED sub-node properties:
- gpios : Should specify the LED's GPIO, see "Specifying GPIO information
for devices" in Documentation/devicetree/booting-without-of.txt. Active
low LEDs should be indicated using flags in the GPIO specifier.
- gpios : Should specify the LED's GPIO, see "gpios property" in
Documentation/devicetree/gpio.txt. Active low LEDs should be
indicated using flags in the GPIO specifier.
- label : (optional) The label for this LED. If omitted, the label is
taken from the node name (excluding the unit address).
- linux,default-trigger : (optional) This parameter, if present, is a

1
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -30,6 +30,7 @@ national National Semiconductor
nintendo Nintendo
nvidia NVIDIA
nxp NXP Semiconductors
picochip Picochip Ltd
powervr Imagination Technologies
qcom Qualcomm, Inc.
ramtron Ramtron International

26
Documentation/hwmon/jc42
View File

@ -7,21 +7,29 @@ Supported chips:
Addresses scanned: I2C 0x18 - 0x1f
Datasheets:
http://www.analog.com/static/imported-files/data_sheets/ADT7408.pdf
* IDT TSE2002B3, TS3000B3
Prefix: 'tse2002b3', 'ts3000b3'
* Atmel AT30TS00
Prefix: 'at30ts00'
Addresses scanned: I2C 0x18 - 0x1f
Datasheets:
http://www.idt.com/products/getdoc.cfm?docid=18715691
http://www.idt.com/products/getdoc.cfm?docid=18715692
http://www.atmel.com/Images/doc8585.pdf
* IDT TSE2002B3, TSE2002GB2, TS3000B3, TS3000GB2
Prefix: 'tse2002', 'ts3000'
Addresses scanned: I2C 0x18 - 0x1f
Datasheets:
http://www.idt.com/sites/default/files/documents/IDT_TSE2002B3C_DST_20100512_120303152056.pdf
http://www.idt.com/sites/default/files/documents/IDT_TSE2002GB2A1_DST_20111107_120303145914.pdf
http://www.idt.com/sites/default/files/documents/IDT_TS3000B3A_DST_20101129_120303152013.pdf
http://www.idt.com/sites/default/files/documents/IDT_TS3000GB2A1_DST_20111104_120303151012.pdf
* Maxim MAX6604
Prefix: 'max6604'
Addresses scanned: I2C 0x18 - 0x1f
Datasheets:
http://datasheets.maxim-ic.com/en/ds/MAX6604.pdf
* Microchip MCP9805, MCP98242, MCP98243, MCP9843
Prefixes: 'mcp9805', 'mcp98242', 'mcp98243', 'mcp9843'
* Microchip MCP9804, MCP9805, MCP98242, MCP98243, MCP9843
Prefixes: 'mcp9804', 'mcp9805', 'mcp98242', 'mcp98243', 'mcp9843'
Addresses scanned: I2C 0x18 - 0x1f
Datasheets:
http://ww1.microchip.com/downloads/en/DeviceDoc/22203C.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/21977b.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/21996a.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/22153c.pdf
@ -48,6 +56,12 @@ Supported chips:
Datasheets:
http://www.st.com/stonline/products/literature/ds/13447/stts424.pdf
http://www.st.com/stonline/products/literature/ds/13448/stts424e02.pdf
* ST Microelectronics STTS2002, STTS3000
Prefix: 'stts2002', 'stts3000'
Addresses scanned: I2C 0x18 - 0x1f
Datasheets:
http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00225278.pdf
http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/CD00270920.pdf
* JEDEC JC 42.4 compliant temperature sensor chips
Prefix: 'jc42'
Addresses scanned: I2C 0x18 - 0x1f

3
Documentation/input/alps.txt
View File

@ -13,7 +13,8 @@ Detection
All ALPS touchpads should respond to the "E6 report" command sequence:
E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
00-00-64.
00-00-64 if no buttons are pressed. The bits 0-2 of the first byte will be 1s
if some buttons are pressed.
If the E6 report is successful, the touchpad model is identified using the "E7
report" sequence: E8-E7-E7-E7-E9. The response is the model signature and is

6
Documentation/kernel-parameters.txt
View File

@ -2211,6 +2211,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
default: off.
printk.always_kmsg_dump=
Trigger kmsg_dump for cases other than kernel oops or
panics
Format: <bool> (1/Y/y=enable, 0/N/n=disable)
default: disabled
printk.time= Show timing data prefixed to each printk message line
Format: <bool> (1/Y/y=enable, 0/N/n=disable)

6
MAINTAINERS
View File

@ -962,7 +962,7 @@ F: drivers/tty/serial/msm_serial.c
F: drivers/platform/msm/
F: drivers/*/pm8???-*
F: include/linux/mfd/pm8xxx/
T: git git://codeaurora.org/quic/kernel/davidb/linux-msm.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm.git
S: Maintained
ARM/TOSA MACHINE SUPPORT
@ -1310,7 +1310,7 @@ F: drivers/atm/
F: include/linux/atm*
ATMEL AT91 MCI DRIVER
M: Nicolas Ferre <nicolas.ferre@atmel.com>
M: Ludovic Desroches <ludovic.desroches@atmel.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.atmel.com/products/AT91/
W: http://www.at91.com/
@ -1318,7 +1318,7 @@ S: Maintained
F: drivers/mmc/host/at91_mci.c
ATMEL AT91 / AT32 MCI DRIVER
M: Nicolas Ferre <nicolas.ferre@atmel.com>
M: Ludovic Desroches <ludovic.desroches@atmel.com>
S: Maintained
F: drivers/mmc/host/atmel-mci.c
F: drivers/mmc/host/atmel-mci-regs.h

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 3
SUBLEVEL = 0
EXTRAVERSION = -rc6
EXTRAVERSION = -rc7
NAME = Saber-toothed Squirrel
# *DOCUMENTATION*

2
arch/alpha/include/asm/futex.h
View File

@ -108,7 +108,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
" lda $31,3b-2b(%0)\n"
" .previous\n"
: "+r"(ret), "=&r"(prev), "=&r"(cmp)
: "r"(uaddr), "r"((long)oldval), "r"(newval)
: "r"(uaddr), "r"((long)(int)oldval), "r"(newval)
: "memory");
*uval = prev;

2
arch/arm/Kconfig
View File

@ -1281,7 +1281,7 @@ config ARM_ERRATA_743622
depends on CPU_V7
help
This option enables the workaround for the 743622 Cortex-A9
(r2p0..r2p2) erratum. Under very rare conditions, a faulty
(r2p*) erratum. Under very rare conditions, a faulty
optimisation in the Cortex-A9 Store Buffer may lead to data
corruption. This workaround sets a specific bit in the diagnostic
register of the Cortex-A9 which disables the Store Buffer

1
arch/arm/boot/.gitignore vendored
View File

@ -3,3 +3,4 @@ zImage
xipImage
bootpImage
uImage
*.dtb

2
arch/arm/include/asm/pmu.h
View File

@ -134,7 +134,7 @@ int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
u64 armpmu_event_update(struct perf_event *event,
struct hw_perf_event *hwc,
int idx, int overflow);
int idx);
int armpmu_event_set_period(struct perf_event *event,
struct hw_perf_event *hwc,

1
arch/arm/kernel/ecard.c
View File

@ -242,6 +242,7 @@ static void ecard_init_pgtables(struct mm_struct *mm)
memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (EASI_SIZE / PGDIR_SIZE));
vma.vm_flags = VM_EXEC;
vma.vm_mm = mm;
flush_tlb_range(&vma, IO_START, IO_START + IO_SIZE);

45
arch/arm/kernel/perf_event.c
View File

@ -180,7 +180,7 @@ armpmu_event_set_period(struct perf_event *event,
u64
armpmu_event_update(struct perf_event *event,
struct hw_perf_event *hwc,
int idx, int overflow)
int idx)
{
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
u64 delta, prev_raw_count, new_raw_count;
@ -193,13 +193,7 @@ armpmu_event_update(struct perf_event *event,
new_raw_count) != prev_raw_count)
goto again;
new_raw_count &= armpmu->max_period;
prev_raw_count &= armpmu->max_period;
if (overflow)
delta = armpmu->max_period - prev_raw_count + new_raw_count + 1;
else
delta = new_raw_count - prev_raw_count;
delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
local64_add(delta, &event->count);
local64_sub(delta, &hwc->period_left);
@ -216,7 +210,7 @@ armpmu_read(struct perf_event *event)
if (hwc->idx < 0)
return;
armpmu_event_update(event, hwc, hwc->idx, 0);
armpmu_event_update(event, hwc, hwc->idx);
}
static void
@ -232,7 +226,7 @@ armpmu_stop(struct perf_event *event, int flags)
if (!(hwc->state & PERF_HES_STOPPED)) {
armpmu->disable(hwc, hwc->idx);
barrier(); /* why? */
armpmu_event_update(event, hwc, hwc->idx, 0);
armpmu_event_update(event, hwc, hwc->idx);
hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
}
}
@ -518,7 +512,13 @@ __hw_perf_event_init(struct perf_event *event)
hwc->config_base |= (unsigned long)mapping;
if (!hwc->sample_period) {
hwc->sample_period = armpmu->max_period;
/*
* For non-sampling runs, limit the sample_period to half
* of the counter width. That way, the new counter value
* is far less likely to overtake the previous one unless
* you have some serious IRQ latency issues.
*/
hwc->sample_period = armpmu->max_period >> 1;
hwc->last_period = hwc->sample_period;
local64_set(&hwc->period_left, hwc->sample_period);
}
@ -679,6 +679,28 @@ static void __init cpu_pmu_init(struct arm_pmu *armpmu)
armpmu->type = ARM_PMU_DEVICE_CPU;
}
/*
* PMU hardware loses all context when a CPU goes offline.
* When a CPU is hotplugged back in, since some hardware registers are
* UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
* junk values out of them.
*/
static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
unsigned long action, void *hcpu)
{
if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
return NOTIFY_DONE;
if (cpu_pmu && cpu_pmu->reset)
cpu_pmu->reset(NULL);
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
.notifier_call = pmu_cpu_notify,
};
/*
* CPU PMU identification and registration.
*/
@ -730,6 +752,7 @@ init_hw_perf_events(void)
pr_info("enabled with %s PMU driver, %d counters available\n",
cpu_pmu->name, cpu_pmu->num_events);
cpu_pmu_init(cpu_pmu);
register_cpu_notifier(&pmu_cpu_notifier);
armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
} else {
pr_info("no hardware support available\n");

22
arch/arm/kernel/perf_event_v6.c
View File

@ -467,23 +467,6 @@ armv6pmu_enable_event(struct hw_perf_event *hwc,
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
}
static int counter_is_active(unsigned long pmcr, int idx)
{
unsigned long mask = 0;
if (idx == ARMV6_CYCLE_COUNTER)
mask = ARMV6_PMCR_CCOUNT_IEN;
else if (idx == ARMV6_COUNTER0)
mask = ARMV6_PMCR_COUNT0_IEN;
else if (idx == ARMV6_COUNTER1)
mask = ARMV6_PMCR_COUNT1_IEN;
if (mask)
return pmcr & mask;
WARN_ONCE(1, "invalid counter number (%d)\n", idx);
return 0;
}
static irqreturn_t
armv6pmu_handle_irq(int irq_num,
void *dev)
@ -513,7 +496,8 @@ armv6pmu_handle_irq(int irq_num,
struct perf_event *event = cpuc->events[idx];
struct hw_perf_event *hwc;
if (!counter_is_active(pmcr, idx))
/* Ignore if we don't have an event. */
if (!event)
continue;
/*
@ -524,7 +508,7 @@ armv6pmu_handle_irq(int irq_num,
continue;
hwc = &event->hw;
armpmu_event_update(event, hwc, idx, 1);
armpmu_event_update(event, hwc, idx);
data.period = event->hw.last_period;
if (!armpmu_event_set_period(event, hwc, idx))
continue;

11
arch/arm/kernel/perf_event_v7.c
View File

@ -809,6 +809,11 @@ static inline int armv7_pmnc_disable_intens(int idx)
counter = ARMV7_IDX_TO_COUNTER(idx);
asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter)));
isb();
/* Clear the overflow flag in case an interrupt is pending. */
asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter)));
isb();
return idx;
}
@ -955,6 +960,10 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
struct perf_event *event = cpuc->events[idx];
struct hw_perf_event *hwc;
/* Ignore if we don't have an event. */
if (!event)
continue;
/*
* We have a single interrupt for all counters. Check that
* each counter has overflowed before we process it.
@ -963,7 +972,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
continue;
hwc = &event->hw;
armpmu_event_update(event, hwc, idx, 1);
armpmu_event_update(event, hwc, idx);
data.period = event->hw.last_period;
if (!armpmu_event_set_period(event, hwc, idx))
continue;

20
arch/arm/kernel/perf_event_xscale.c
View File

@ -255,11 +255,14 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
struct perf_event *event = cpuc->events[idx];
struct hw_perf_event *hwc;
if (!event)
continue;
if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
continue;
hwc = &event->hw;
armpmu_event_update(event, hwc, idx, 1);
armpmu_event_update(event, hwc, idx);
data.period = event->hw.last_period;
if (!armpmu_event_set_period(event, hwc, idx))
continue;
@ -592,11 +595,14 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
struct perf_event *event = cpuc->events[idx];
struct hw_perf_event *hwc;
if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))
if (!event)
continue;
if (!xscale2_pmnc_counter_has_overflowed(of_flags, idx))
continue;
hwc = &event->hw;
armpmu_event_update(event, hwc, idx, 1);
armpmu_event_update(event, hwc, idx);
data.period = event->hw.last_period;
if (!armpmu_event_set_period(event, hwc, idx))
continue;
@ -663,7 +669,7 @@ xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
static void
xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
{
unsigned long flags, ien, evtsel;
unsigned long flags, ien, evtsel, of_flags;
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
ien = xscale2pmu_read_int_enable();
@ -672,26 +678,31 @@ xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
switch (idx) {
case XSCALE_CYCLE_COUNTER:
ien &= ~XSCALE2_CCOUNT_INT_EN;
of_flags = XSCALE2_CCOUNT_OVERFLOW;
break;
case XSCALE_COUNTER0:
ien &= ~XSCALE2_COUNT0_INT_EN;
evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
of_flags = XSCALE2_COUNT0_OVERFLOW;
break;
case XSCALE_COUNTER1:
ien &= ~XSCALE2_COUNT1_INT_EN;
evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
of_flags = XSCALE2_COUNT1_OVERFLOW;
break;
case XSCALE_COUNTER2:
ien &= ~XSCALE2_COUNT2_INT_EN;
evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
of_flags = XSCALE2_COUNT2_OVERFLOW;
break;
case XSCALE_COUNTER3:
ien &= ~XSCALE2_COUNT3_INT_EN;
evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
of_flags = XSCALE2_COUNT3_OVERFLOW;
break;
default:
WARN_ONCE(1, "invalid counter number (%d)\n", idx);
@ -701,6 +712,7 @@ xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
raw_spin_lock_irqsave(&events->pmu_lock, flags);
xscale2pmu_write_event_select(evtsel);
xscale2pmu_write_int_enable(ien);
xscale2pmu_write_overflow_flags(of_flags);
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
}

19
arch/arm/mach-at91/at91sam9g45_devices.c
View File

@ -38,10 +38,6 @@
#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
static u64 hdmac_dmamask = DMA_BIT_MASK(32);
static struct at_dma_platform_data atdma_pdata = {
.nr_channels = 8,
};
static struct resource hdmac_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_DMA,
@ -56,12 +52,11 @@ static struct resource hdmac_resources[] = {
};
static struct platform_device at_hdmac_device = {
.name = "at_hdmac",
.name = "at91sam9g45_dma",
.id = -1,
.dev = {
.dma_mask = &hdmac_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &atdma_pdata,
},
.resource = hdmac_resources,
.num_resources = ARRAY_SIZE(hdmac_resources),
@ -69,9 +64,15 @@ static struct platform_device at_hdmac_device = {
void __init at91_add_device_hdmac(void)
{
dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
platform_device_register(&at_hdmac_device);
#if defined(CONFIG_OF)
struct device_node *of_node =
of_find_node_by_name(NULL, "dma-controller");
if (of_node)
of_node_put(of_node);
else
#endif
platform_device_register(&at_hdmac_device);
}
#else
void __init at91_add_device_hdmac(void) {}

8
arch/arm/mach-at91/at91sam9rl_devices.c
View File

@ -33,10 +33,6 @@
#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
static u64 hdmac_dmamask = DMA_BIT_MASK(32);
static struct at_dma_platform_data atdma_pdata = {
.nr_channels = 2,
};
static struct resource hdmac_resources[] = {
[0] = {
.start = AT91SAM9RL_BASE_DMA,
@ -51,12 +47,11 @@ static struct resource hdmac_resources[] = {
};
static struct platform_device at_hdmac_device = {
.name = "at_hdmac",
.name = "at91sam9rl_dma",
.id = -1,
.dev = {
.dma_mask = &hdmac_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &atdma_pdata,
},
.resource = hdmac_resources,
.num_resources = ARRAY_SIZE(hdmac_resources),
@ -64,7 +59,6 @@ static struct platform_device at_hdmac_device = {
void __init at91_add_device_hdmac(void)
{
dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
platform_device_register(&at_hdmac_device);
}
#else

2
arch/arm/mach-ep93xx/vision_ep9307.c
View File

@ -34,6 +34,7 @@
#include <mach/ep93xx_spi.h>
#include <mach/gpio-ep93xx.h>
#include <asm/hardware/vic.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
@ -361,6 +362,7 @@ MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
.atag_offset = 0x100,
.map_io = vision_map_io,
.init_irq = ep93xx_init_irq,
.handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = vision_init_machine,
.restart = ep93xx_restart,

2
arch/arm/mach-exynos/mach-universal_c210.c
View File

@ -13,6 +13,7 @@
#include <linux/i2c.h>
#include <linux/gpio_keys.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/mfd/max8998.h>
#include <linux/regulator/machine.h>
@ -595,6 +596,7 @@ static struct mxt_platform_data qt602240_platform_data = {
.threshold = 0x28,
.voltage = 2800000, /* 2.8V */
.orient = MXT_DIAGONAL,
.irqflags = IRQF_TRIGGER_FALLING,
};
static struct i2c_board_info i2c3_devs[] __initdata = {

1
arch/arm/mach-omap2/id.c
View File

@ -396,6 +396,7 @@ void __init omap3xxx_check_revision(void)
case 0xb944:
omap_revision = AM335X_REV_ES1_0;
cpu_rev = "1.0";
break;
case 0xb8f2:
switch (rev) {
case 0:

3
arch/arm/mach-omap2/mailbox.c
View File

@ -420,8 +420,7 @@ static void __exit omap2_mbox_exit(void)
platform_driver_unregister(&omap2_mbox_driver);
}
/* must be ready before omap3isp is probed */
subsys_initcall(omap2_mbox_init);
module_init(omap2_mbox_init);
module_exit(omap2_mbox_exit);
MODULE_LICENSE("GPL v2");

3
arch/arm/mach-omap2/omap-iommu.c
View File

@ -150,7 +150,8 @@ static int __init omap_iommu_init(void)
platform_device_put(omap_iommu_pdev[i]);
return err;
}
module_init(omap_iommu_init);
/* must be ready before omap3isp is probed */
subsys_initcall(omap_iommu_init);
static void __exit omap_iommu_exit(void)
{

2
arch/arm/mach-omap2/omap4-common.c
View File

@ -31,6 +31,7 @@
#include "common.h"
#include "omap4-sar-layout.h"
#include <linux/export.h>
#ifdef CONFIG_CACHE_L2X0
static void __iomem *l2cache_base;
@ -55,6 +56,7 @@ void omap_bus_sync(void)
isb();
}
}
EXPORT_SYMBOL(omap_bus_sync);
/* Steal one page physical memory for barrier implementation */
int __init omap_barrier_reserve_memblock(void)

1
arch/arm/mach-omap2/twl-common.c
View File

@ -270,7 +270,6 @@ static struct regulator_init_data omap4_vusb_idata = {
.constraints = {
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE

1
arch/arm/mach-pxa/generic.h
View File

@ -49,7 +49,6 @@ extern unsigned pxa3xx_get_clk_frequency_khz(int);
#endif
extern struct syscore_ops pxa_irq_syscore_ops;
extern struct syscore_ops pxa_gpio_syscore_ops;
extern struct syscore_ops pxa2xx_mfp_syscore_ops;
extern struct syscore_ops pxa3xx_mfp_syscore_ops;

7
arch/arm/mach-pxa/mfp-pxa2xx.c
View File

@ -226,6 +226,12 @@ static void __init pxa25x_mfp_init(void)
{
int i;
/* running before pxa_gpio_probe() */
#ifdef CONFIG_CPU_PXA26x
pxa_last_gpio = 89;
#else
pxa_last_gpio = 84;
#endif
for (i = 0; i <= pxa_last_gpio; i++)
gpio_desc[i].valid = 1;
@ -295,6 +301,7 @@ static void __init pxa27x_mfp_init(void)
{
int i, gpio;
pxa_last_gpio = 120; /* running before pxa_gpio_probe() */
for (i = 0; i <= pxa_last_gpio; i++) {
/* skip GPIO2, 5, 6, 7, 8, they are not
* valid pins allow configuration

2
arch/arm/mach-pxa/pxa25x.c
View File

@ -208,6 +208,7 @@ static struct clk_lookup pxa25x_clkregs[] = {
INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
};
static struct clk_lookup pxa25x_hwuart_clkreg =
@ -367,7 +368,6 @@ static int __init pxa25x_init(void)
register_syscore_ops(&pxa_irq_syscore_ops);
register_syscore_ops(&pxa2xx_mfp_syscore_ops);
register_syscore_ops(&pxa_gpio_syscore_ops);
register_syscore_ops(&pxa2xx_clock_syscore_ops);
ret = platform_add_devices(pxa25x_devices,

2
arch/arm/mach-pxa/pxa27x.c
View File

@ -229,6 +229,7 @@ static struct clk_lookup pxa27x_clkregs[] = {
INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
};
#ifdef CONFIG_PM
@ -455,7 +456,6 @@ static int __init pxa27x_init(void)
register_syscore_ops(&pxa_irq_syscore_ops);
register_syscore_ops(&pxa2xx_mfp_syscore_ops);
register_syscore_ops(&pxa_gpio_syscore_ops);
register_syscore_ops(&pxa2xx_clock_syscore_ops);
ret = platform_add_devices(devices, ARRAY_SIZE(devices));

1
arch/arm/mach-pxa/pxa3xx.c
View File

@ -462,7 +462,6 @@ static int __init pxa3xx_init(void)
register_syscore_ops(&pxa_irq_syscore_ops);
register_syscore_ops(&pxa3xx_mfp_syscore_ops);
register_syscore_ops(&pxa_gpio_syscore_ops);
register_syscore_ops(&pxa3xx_clock_syscore_ops);
ret = platform_add_devices(devices, ARRAY_SIZE(devices));

1
arch/arm/mach-pxa/pxa95x.c
View File

@ -283,7 +283,6 @@ static int __init pxa95x_init(void)
return ret;
register_syscore_ops(&pxa_irq_syscore_ops);
register_syscore_ops(&pxa_gpio_syscore_ops);
register_syscore_ops(&pxa3xx_clock_syscore_ops);
ret = platform_add_devices(devices, ARRAY_SIZE(devices));

2
arch/arm/mach-s3c2440/common.h
View File

@ -12,6 +12,6 @@
#ifndef __ARCH_ARM_MACH_S3C2440_COMMON_H
#define __ARCH_ARM_MACH_S3C2440_COMMON_H
void s3c2440_restart(char mode, const char *cmd);
void s3c244x_restart(char mode, const char *cmd);
#endif /* __ARCH_ARM_MACH_S3C2440_COMMON_H */

2
arch/arm/mach-s3c2440/mach-anubis.c
View File

@ -487,5 +487,5 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
.init_machine = anubis_init,
.init_irq = s3c24xx_init_irq,
.timer = &s3c24xx_timer,
.restart = s3c2440_restart,
.restart = s3c244x_restart,
MACHINE_END

2
arch/arm/mach-s3c2440/mach-at2440evb.c
View File

@ -222,5 +222,5 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
.init_machine = at2440evb_init,
.init_irq = s3c24xx_init_irq,
.timer = &s3c24xx_timer,
.restart = s3c2440_restart,
.restart = s3c244x_restart,
MACHINE_END

2
arch/arm/mach-s3c2440/mach-gta02.c
View File

@ -601,5 +601,5 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
.init_irq = s3c24xx_init_irq,
.init_machine = gta02_machine_init,
.timer = &s3c24xx_timer,
.restart = s3c2440_restart,
.restart = s3c244x_restart,
MACHINE_END

2
arch/arm/mach-s3c2440/mach-mini2440.c
View File

@ -701,5 +701,5 @@ MACHINE_START(MINI2440, "MINI2440")
.init_machine = mini2440_init,
.init_irq = s3c24xx_init_irq,
.timer = &s3c24xx_timer,
.restart = s3c2440_restart,
.restart = s3c244x_restart,
MACHINE_END

2
arch/arm/mach-s3c2440/mach-nexcoder.c
View File

@ -158,5 +158,5 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
.init_machine = nexcoder_init,
.init_irq = s3c24xx_init_irq,
.timer = &s3c24xx_timer,
.restart = s3c2440_restart,
.restart = s3c244x_restart,
MACHINE_END

2
arch/arm/mach-s3c2440/mach-osiris.c
View File

@ -436,5 +436,5 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
.init_irq = s3c24xx_init_irq,
.init_machine = osiris_init,
.timer = &s3c24xx_timer,
.restart = s3c2440_restart,
.restart = s3c244x_restart,
MACHINE_END

2
arch/arm/mach-s3c2440/mach-rx1950.c
View File

@ -822,5 +822,5 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
.init_irq = s3c24xx_init_irq,
.init_machine = rx1950_init_machine,
.timer = &s3c24xx_timer,
.restart = s3c2440_restart,
.restart = s3c244x_restart,
MACHINE_END

2
arch/arm/mach-s3c2440/mach-rx3715.c
View File

@ -213,5 +213,5 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
.init_irq = rx3715_init_irq,
.init_machine = rx3715_init_machine,
.timer = &s3c24xx_timer,
.restart = s3c2440_restart,
.restart = s3c244x_restart,
MACHINE_END

2
arch/arm/mach-s3c2440/mach-smdk2440.c
View File

@ -183,5 +183,5 @@ MACHINE_START(S3C2440, "SMDK2440")
.map_io = smdk2440_map_io,
.init_machine = smdk2440_machine_init,
.timer = &s3c24xx_timer,
.restart = s3c2440_restart,
.restart = s3c244x_restart,
MACHINE_END

13
arch/arm/mach-s3c2440/s3c2440.c
View File

@ -35,7 +35,6 @@
#include <plat/cpu.h>
#include <plat/s3c244x.h>
#include <plat/pm.h>
#include <plat/watchdog-reset.h>
#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
@ -74,15 +73,3 @@ void __init s3c2440_map_io(void)
s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
}
void s3c2440_restart(char mode, const char *cmd)
{
if (mode == 's') {
soft_restart(0);
}
arch_wdt_reset();
/* we'll take a jump through zero as a poor second */
soft_restart(0);
}

12
arch/arm/mach-s3c2440/s3c244x.c
View File

@ -46,6 +46,7 @@
#include <plat/pm.h>
#include <plat/pll.h>
#include <plat/nand-core.h>
#include <plat/watchdog-reset.h>
static struct map_desc s3c244x_iodesc[] __initdata = {
IODESC_ENT(CLKPWR),
@ -196,3 +197,14 @@ struct syscore_ops s3c244x_pm_syscore_ops = {
.suspend = s3c244x_suspend,
.resume = s3c244x_resume,
};
void s3c244x_restart(char mode, const char *cmd)
{
if (mode == 's')
soft_restart(0);
arch_wdt_reset();
/* we'll take a jump through zero as a poor second */
soft_restart(0);
}

39
arch/arm/mach-shmobile/board-ag5evm.c
View File

@ -46,8 +46,6 @@
#include <mach/common.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/traps.h>
@ -486,27 +484,6 @@ static struct platform_device *ag5evm_devices[] __initdata = {
&sdhi1_device,
};
static struct map_desc ag5evm_io_desc[] __initdata = {
/* create a 1:1 entity map for 0xe6xxxxxx
* used by CPGA, INTC and PFC.
*/
{
.virtual = 0xe6000000,
.pfn = __phys_to_pfn(0xe6000000),
.length = 256 << 20,
.type = MT_DEVICE_NONSHARED
},
};
static void __init ag5evm_map_io(void)
{
iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc));
/* setup early devices and console here as well */
sh73a0_add_early_devices();
shmobile_setup_console();
}
static void __init ag5evm_init(void)
{
sh73a0_pinmux_init();
@ -622,22 +599,12 @@ static void __init ag5evm_init(void)
platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices));
}
static void __init ag5evm_timer_init(void)
{
sh73a0_clock_init();
shmobile_timer.init();
return;
}
struct sys_timer ag5evm_timer = {
.init = ag5evm_timer_init,
};
MACHINE_START(AG5EVM, "ag5evm")
.map_io = ag5evm_map_io,
.map_io = sh73a0_map_io,
.init_early = sh73a0_add_early_devices,
.nr_irqs = NR_IRQS_LEGACY,
.init_irq = sh73a0_init_irq,
.handle_irq = gic_handle_irq,
.init_machine = ag5evm_init,
.timer = &ag5evm_timer,
.timer = &shmobile_timer,
MACHINE_END

44
arch/arm/mach-shmobile/board-ap4evb.c
View File

@ -61,8 +61,6 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/setup.h>
/*
@ -1190,27 +1188,6 @@ static struct i2c_board_info i2c1_devices[] = {
},
};
static struct map_desc ap4evb_io_desc[] __initdata = {
/* create a 1:1 entity map for 0xe6xxxxxx
* used by CPGA, INTC and PFC.
*/
{
.virtual = 0xe6000000,
.pfn = __phys_to_pfn(0xe6000000),
.length = 256 << 20,
.type = MT_DEVICE_NONSHARED
},
};
static void __init ap4evb_map_io(void)
{
iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc));
/* setup early devices and console here as well */
sh7372_add_early_devices();
shmobile_setup_console();
}
#define GPIO_PORT9CR 0xE6051009
#define GPIO_PORT10CR 0xE605100A
#define USCCR1 0xE6058144
@ -1219,6 +1196,9 @@ static void __init ap4evb_init(void)
u32 srcr4;
struct clk *clk;
/* External clock source */
clk_set_rate(&sh7372_dv_clki_clk, 27000000);
sh7372_pinmux_init();
/* enable SCIFA0 */
@ -1455,23 +1435,11 @@ static void __init ap4evb_init(void)
pm_clk_add(&lcdc1_device.dev, "hdmi");
}
static void __init ap4evb_timer_init(void)
{
sh7372_clock_init();
shmobile_timer.init();
/* External clock source */
clk_set_rate(&sh7372_dv_clki_clk, 27000000);
}
static struct sys_timer ap4evb_timer = {
.init = ap4evb_timer_init,
};
MACHINE_START(AP4EVB, "ap4evb")
.map_io = ap4evb_map_io,
.map_io = sh7372_map_io,
.init_early = sh7372_add_early_devices,
.init_irq = sh7372_init_irq,
.handle_irq = shmobile_handle_irq_intc,
.init_machine = ap4evb_init,
.timer = &ap4evb_timer,
.timer = &shmobile_timer,
MACHINE_END

44
arch/arm/mach-shmobile/board-bonito.c
View File

@ -327,28 +327,6 @@ static struct platform_device *bonito_base_devices[] __initdata = {
* map I/O
*/
static struct map_desc bonito_io_desc[] __initdata = {
/*
* for CPGA/INTC/PFC
* 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
*/
{
.virtual = 0xe6000000,
.pfn = __phys_to_pfn(0xe6000000),
.length = 160 << 20,
.type = MT_DEVICE_NONSHARED
},
#ifdef CONFIG_CACHE_L2X0
/*
* for l2x0_init()
* 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
*/
{
.virtual = 0xf0002000,
.pfn = __phys_to_pfn(0xf0100000),
.length = PAGE_SIZE,
.type = MT_DEVICE_NONSHARED
},
#endif
/*
* for FPGA (0x1800000-0x19ffffff)
* 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
@ -363,11 +341,8 @@ static struct map_desc bonito_io_desc[] __initdata = {
static void __init bonito_map_io(void)
{
r8a7740_map_io();
iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
/* setup early devices and console here as well */
r8a7740_add_early_devices();
shmobile_setup_console();
}
/*
@ -491,7 +466,7 @@ static void __init bonito_init(void)
}
}
static void __init bonito_timer_init(void)
static void __init bonito_earlytimer_init(void)
{
u16 val;
u8 md_ck = 0;
@ -506,17 +481,22 @@ static void __init bonito_timer_init(void)
md_ck |= MD_CK0;
r8a7740_clock_init(md_ck);
shmobile_timer.init();
shmobile_earlytimer_init();
}
struct sys_timer bonito_timer = {
.init = bonito_timer_init,
};
void __init bonito_add_early_devices(void)
{
r8a7740_add_early_devices();
/* override timer setup with board-specific code */
shmobile_timer.init = bonito_earlytimer_init;
}
MACHINE_START(BONITO, "bonito")
.map_io = bonito_map_io,
.init_early = bonito_add_early_devices,
.init_irq = r8a7740_init_irq,
.handle_irq = shmobile_handle_irq_intc,
.init_machine = bonito_init,
.timer = &bonito_timer,
.timer = &shmobile_timer,
MACHINE_END

38
arch/arm/mach-shmobile/board-g3evm.c
View File

@ -37,8 +37,6 @@
#include <mach/common.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
/*
* IrDA
@ -246,27 +244,6 @@ static struct platform_device *g3evm_devices[] __initdata = {
&irda_device,
};
static struct map_desc g3evm_io_desc[] __initdata = {
/* create a 1:1 entity map for 0xe6xxxxxx
* used by CPGA, INTC and PFC.
*/
{
.virtual = 0xe6000000,
.pfn = __phys_to_pfn(0xe6000000),
.length = 256 << 20,
.type = MT_DEVICE_NONSHARED
},
};
static void __init g3evm_map_io(void)
{
iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc));
/* setup early devices and console here as well */
sh7367_add_early_devices();
shmobile_setup_console();
}
static void __init g3evm_init(void)
{
sh7367_pinmux_init();
@ -354,20 +331,11 @@ static void __init g3evm_init(void)
platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices));
}
static void __init g3evm_timer_init(void)
{
sh7367_clock_init();
shmobile_timer.init();
}
static struct sys_timer g3evm_timer = {
.init = g3evm_timer_init,
};
MACHINE_START(G3EVM, "g3evm")
.map_io = g3evm_map_io,
.map_io = sh7367_map_io,
.init_early = sh7367_add_early_devices,
.init_irq = sh7367_init_irq,
.handle_irq = shmobile_handle_irq_intc,
.init_machine = g3evm_init,
.timer = &g3evm_timer,
.timer = &shmobile_timer,
MACHINE_END

38
arch/arm/mach-shmobile/board-g4evm.c
View File

@ -38,8 +38,6 @@
#include <mach/common.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
/*
* SDHI
@ -260,27 +258,6 @@ static struct platform_device *g4evm_devices[] __initdata = {
&sdhi1_device,
};
static struct map_desc g4evm_io_desc[] __initdata = {
/* create a 1:1 entity map for 0xe6xxxxxx
* used by CPGA, INTC and PFC.
*/
{
.virtual = 0xe6000000,
.pfn = __phys_to_pfn(0xe6000000),
.length = 256 << 20,
.type = MT_DEVICE_NONSHARED
},
};
static void __init g4evm_map_io(void)
{
iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc));
/* setup early devices and console here as well */
sh7377_add_early_devices();
shmobile_setup_console();
}
#define GPIO_SDHID0_D0 0xe60520fc
#define GPIO_SDHID0_D1 0xe60520fd
#define GPIO_SDHID0_D2 0xe60520fe
@ -397,20 +374,11 @@ static void __init g4evm_init(void)
platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices));
}
static void __init g4evm_timer_init(void)
{
sh7377_clock_init();
shmobile_timer.init();
}
static struct sys_timer g4evm_timer = {
.init = g4evm_timer_init,
};
MACHINE_START(G4EVM, "g4evm")
.map_io = g4evm_map_io,
.map_io = sh7377_map_io,
.init_early = sh7377_add_early_devices,
.init_irq = sh7377_init_irq,
.handle_irq = shmobile_handle_irq_intc,
.init_machine = g4evm_init,
.timer = &g4evm_timer,
.timer = &shmobile_timer,
MACHINE_END

38
arch/arm/mach-shmobile/board-kota2.c
View File

@ -43,7 +43,6 @@
#include <mach/common.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
@ -409,27 +408,6 @@ static struct platform_device *kota2_devices[] __initdata = {
&sdhi1_device,
};
static struct map_desc kota2_io_desc[] __initdata = {
/* create a 1:1 entity map for 0xe6xxxxxx
* used by CPGA, INTC and PFC.
*/
{
.virtual = 0xe6000000,
.pfn = __phys_to_pfn(0xe6000000),
.length = 256 << 20,
.type = MT_DEVICE_NONSHARED
},
};
static void __init kota2_map_io(void)
{
iotable_init(kota2_io_desc, ARRAY_SIZE(kota2_io_desc));
/* setup early devices and console here as well */
sh73a0_add_early_devices();
shmobile_setup_console();
}
static void __init kota2_init(void)
{
sh73a0_pinmux_init();
@ -535,22 +513,12 @@ static void __init kota2_init(void)
platform_add_devices(kota2_devices, ARRAY_SIZE(kota2_devices));
}
static void __init kota2_timer_init(void)
{
sh73a0_clock_init();
shmobile_timer.init();
return;
}
struct sys_timer kota2_timer = {
.init = kota2_timer_init,
};
MACHINE_START(KOTA2, "kota2")
.map_io = kota2_map_io,
.map_io = sh73a0_map_io,
.init_early = sh73a0_add_early_devices,
.nr_irqs = NR_IRQS_LEGACY,
.init_irq = sh73a0_init_irq,
.handle_irq = gic_handle_irq,
.init_machine = kota2_init,
.timer = &kota2_timer,
.timer = &shmobile_timer,
MACHINE_END

44
arch/arm/mach-shmobile/board-mackerel.c
View File

@ -57,8 +57,6 @@
#include <mach/sh7372.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <asm/mach-types.h>
/*
@ -1337,27 +1335,6 @@ static struct i2c_board_info i2c1_devices[] = {
},
};
static struct map_desc mackerel_io_desc[] __initdata = {
/* create a 1:1 entity map for 0xe6xxxxxx
* used by CPGA, INTC and PFC.
*/
{
.virtual = 0xe6000000,
.pfn = __phys_to_pfn(0xe6000000),
.length = 256 << 20,
.type = MT_DEVICE_NONSHARED
},
};
static void __init mackerel_map_io(void)
{
iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc));
/* setup early devices and console here as well */
sh7372_add_early_devices();
shmobile_setup_console();
}
#define GPIO_PORT9CR 0xE6051009
#define GPIO_PORT10CR 0xE605100A
#define GPIO_PORT167CR 0xE60520A7
@ -1370,6 +1347,9 @@ static void __init mackerel_init(void)
struct clk *clk;
int ret;
/* External clock source */
clk_set_rate(&sh7372_dv_clki_clk, 27000000);
sh7372_pinmux_init();
/* enable SCIFA0 */
@ -1573,23 +1553,11 @@ static void __init mackerel_init(void)
pm_clk_add(&hdmi_lcdc_device.dev, "hdmi");
}
static void __init mackerel_timer_init(void)
{
sh7372_clock_init();
shmobile_timer.init();
/* External clock source */
clk_set_rate(&sh7372_dv_clki_clk, 27000000);
}
static struct sys_timer mackerel_timer = {
.init = mackerel_timer_init,
};
MACHINE_START(MACKEREL, "mackerel")
.map_io = mackerel_map_io,
.map_io = sh7372_map_io,
.init_early = sh7372_add_early_devices,
.init_irq = sh7372_init_irq,
.handle_irq = shmobile_handle_irq_intc,
.init_machine = mackerel_init,
.timer = &mackerel_timer,
.timer = &shmobile_timer,
MACHINE_END

62
arch/arm/mach-shmobile/board-marzen.c
View File

@ -33,8 +33,6 @@
#include <mach/common.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/hardware/gic.h>
#include <asm/traps.h>
@ -72,49 +70,6 @@ static struct platform_device *marzen_devices[] __initdata = {
&eth_device,
};
static struct map_desc marzen_io_desc[] __initdata = {
/* 2M entity map for 0xf0000000 (MPCORE) */
{
.virtual = 0xf0000000,
.pfn = __phys_to_pfn(0xf0000000),
.length = SZ_2M,
.type = MT_DEVICE_NONSHARED
},
/* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
{
.virtual = 0xfe000000,
.pfn = __phys_to_pfn(0xfe000000),
.length = SZ_16M,
.type = MT_DEVICE_NONSHARED
},
};
static void __init marzen_map_io(void)
{
iotable_init(marzen_io_desc, ARRAY_SIZE(marzen_io_desc));
}
static void __init marzen_init_early(void)
{
r8a7779_add_early_devices();
/* Early serial console setup is not included here due to
* memory map collisions. The SCIF serial ports in r8a7779
* are difficult to entity map 1:1 due to collision with the
* virtual memory range used by the coherent DMA code on ARM.
*
* Anyone wanting to debug early can remove UPF_IOREMAP from
* the sh-sci serial console platform data, adjust mapbase
* to a static M:N virt:phys mapping that needs to be added to
* the mappings passed with iotable_init() above.
*
* Then add a call to shmobile_setup_console() from this function.
*
* As a final step pass earlyprint=sh-sci.2,115200 on the kernel
* command line.
*/
}
static void __init marzen_init(void)
{
r8a7779_pinmux_init();
@ -135,23 +90,12 @@ static void __init marzen_init(void)
platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
}
static void __init marzen_timer_init(void)
{
r8a7779_clock_init();
shmobile_timer.init();
return;
}
struct sys_timer marzen_timer = {
.init = marzen_timer_init,
};
MACHINE_START(MARZEN, "marzen")
.map_io = marzen_map_io,
.init_early = marzen_init_early,
.map_io = r8a7779_map_io,
.init_early = r8a7779_add_early_devices,
.nr_irqs = NR_IRQS_LEGACY,
.init_irq = r8a7779_init_irq,
.handle_irq = gic_handle_irq,
.init_machine = marzen_init,
.timer = &marzen_timer,
.timer = &shmobile_timer,
MACHINE_END

8
arch/arm/mach-shmobile/clock-r8a7740.c
View File

@ -93,7 +93,7 @@ static unsigned long div_recalc(struct clk *clk)
return clk->parent->rate / (int)(clk->priv);
}
static struct clk_ops div_clk_ops = {
static struct sh_clk_ops div_clk_ops = {
.recalc = div_recalc,
};
@ -125,7 +125,7 @@ static struct clk extal2_div2_clk = {
.parent = &extal2_clk,
};
static struct clk_ops followparent_clk_ops = {
static struct sh_clk_ops followparent_clk_ops = {
.recalc = followparent_recalc,
};
@ -156,7 +156,7 @@ static unsigned long pllc01_recalc(struct clk *clk)
return clk->parent->rate * mult;
}
static struct clk_ops pllc01_clk_ops = {
static struct sh_clk_ops pllc01_clk_ops = {
.recalc = pllc01_recalc,
};
@ -376,7 +376,7 @@ void __init r8a7740_clock_init(u8 md_ck)
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
clk_init();
shmobile_clk_init();
else
panic("failed to setup r8a7740 clocks\n");
}

4
arch/arm/mach-shmobile/clock-r8a7779.c
View File

@ -107,7 +107,7 @@ static unsigned long mul4_recalc(struct clk *clk)
return clk->parent->rate * 4;
}
static struct clk_ops mul4_clk_ops = {
static struct sh_clk_ops mul4_clk_ops = {
.recalc = mul4_recalc,
};
@ -170,7 +170,7 @@ void __init r8a7779_clock_init(void)
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
clk_init();
shmobile_clk_init();
else
panic("failed to setup r8a7779 clocks\n");
}

8
arch/arm/mach-shmobile/clock-sh7367.c
View File

@ -74,7 +74,7 @@ static unsigned long div2_recalc(struct clk *clk)
return clk->parent->rate / 2;
}
static struct clk_ops div2_clk_ops = {
static struct sh_clk_ops div2_clk_ops = {
.recalc = div2_recalc,
};
@ -101,7 +101,7 @@ static unsigned long pllc1_recalc(struct clk *clk)
return clk->parent->rate * mult;
}
static struct clk_ops pllc1_clk_ops = {
static struct sh_clk_ops pllc1_clk_ops = {
.recalc = pllc1_recalc,
};
@ -128,7 +128,7 @@ static unsigned long pllc2_recalc(struct clk *clk)
return clk->parent->rate * mult;
}
static struct clk_ops pllc2_clk_ops = {
static struct sh_clk_ops pllc2_clk_ops = {
.recalc = pllc2_recalc,
};
@ -349,7 +349,7 @@ void __init sh7367_clock_init(void)
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
clk_init();
shmobile_clk_init();
else
panic("failed to setup sh7367 clocks\n");
}

10
arch/arm/mach-shmobile/clock-sh7372.c
View File

@ -89,7 +89,7 @@ static unsigned long div2_recalc(struct clk *clk)
return clk->parent->rate / 2;
}
static struct clk_ops div2_clk_ops = {
static struct sh_clk_ops div2_clk_ops = {
.recalc = div2_recalc,
};
@ -128,7 +128,7 @@ static unsigned long pllc01_recalc(struct clk *clk)
return clk->parent->rate * mult;
}
static struct clk_ops pllc01_clk_ops = {
static struct sh_clk_ops pllc01_clk_ops = {
.recalc = pllc01_recalc,
};
@ -276,7 +276,7 @@ static int pllc2_set_parent(struct clk *clk, struct clk *parent)
return 0;
}
static struct clk_ops pllc2_clk_ops = {
static struct sh_clk_ops pllc2_clk_ops = {
.recalc = pllc2_recalc,
.round_rate = pllc2_round_rate,
.set_rate = pllc2_set_rate,
@ -468,7 +468,7 @@ static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
return 0;
}
static struct clk_ops fsidiv_clk_ops = {
static struct sh_clk_ops fsidiv_clk_ops = {
.recalc = fsidiv_recalc,
.round_rate = fsidiv_round_rate,
.set_rate = fsidiv_set_rate,
@ -710,7 +710,7 @@ void __init sh7372_clock_init(void)
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
clk_init();
shmobile_clk_init();
else
panic("failed to setup sh7372 clocks\n");

8
arch/arm/mach-shmobile/clock-sh7377.c
View File

@ -77,7 +77,7 @@ static unsigned long div2_recalc(struct clk *clk)
return clk->parent->rate / 2;
}
static struct clk_ops div2_clk_ops = {
static struct sh_clk_ops div2_clk_ops = {
.recalc = div2_recalc,
};
@ -110,7 +110,7 @@ static unsigned long pllc1_recalc(struct clk *clk)
return clk->parent->rate * mult;
}
static struct clk_ops pllc1_clk_ops = {
static struct sh_clk_ops pllc1_clk_ops = {
.recalc = pllc1_recalc,
};
@ -137,7 +137,7 @@ static unsigned long pllc2_recalc(struct clk *clk)
return clk->parent->rate * mult;
}
static struct clk_ops pllc2_clk_ops = {
static struct sh_clk_ops pllc2_clk_ops = {
.recalc = pllc2_recalc,
};
@ -360,7 +360,7 @@ void __init sh7377_clock_init(void)
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
clk_init();
shmobile_clk_init();
else
panic("failed to setup sh7377 clocks\n");
}

14
arch/arm/mach-shmobile/clock-sh73a0.c
View File

@ -88,7 +88,7 @@ static unsigned long div2_recalc(struct clk *clk)
return clk->parent->rate / 2;
}
static struct clk_ops div2_clk_ops = {
static struct sh_clk_ops div2_clk_ops = {
.recalc = div2_recalc,
};
@ -97,7 +97,7 @@ static unsigned long div7_recalc(struct clk *clk)
return clk->parent->rate / 7;
}
static struct clk_ops div7_clk_ops = {
static struct sh_clk_ops div7_clk_ops = {
.recalc = div7_recalc,
};
@ -106,7 +106,7 @@ static unsigned long div13_recalc(struct clk *clk)
return clk->parent->rate / 13;
}
static struct clk_ops div13_clk_ops = {
static struct sh_clk_ops div13_clk_ops = {
.recalc = div13_recalc,
};
@ -122,7 +122,7 @@ static struct clk extal2_div2_clk = {
.parent = &sh73a0_extal2_clk,
};
static struct clk_ops main_clk_ops = {
static struct sh_clk_ops main_clk_ops = {
.recalc = followparent_recalc,
};
@ -156,7 +156,7 @@ static unsigned long pll_recalc(struct clk *clk)
return clk->parent->rate * mult;
}
static struct clk_ops pll_clk_ops = {
static struct sh_clk_ops pll_clk_ops = {
.recalc = pll_recalc,
};
@ -438,7 +438,7 @@ static int dsiphy_set_rate(struct clk *clk, unsigned long rate)
return 0;
}
static struct clk_ops dsiphy_clk_ops = {
static struct sh_clk_ops dsiphy_clk_ops = {
.recalc = dsiphy_recalc,
.round_rate = dsiphy_round_rate,
.set_rate = dsiphy_set_rate,
@ -620,7 +620,7 @@ void __init sh73a0_clock_init(void)
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
clk_init();
shmobile_clk_init();
else
panic("failed to setup sh73a0 clocks\n");
}

2
arch/arm/mach-shmobile/clock.c
View File

@ -24,7 +24,7 @@
#include <linux/sh_clk.h>
#include <linux/export.h>
int __init clk_init(void)
int __init shmobile_clk_init(void)
{
/* Kick the child clocks.. */
recalculate_root_clocks();

9
arch/arm/mach-shmobile/include/mach/common.h
View File

@ -1,12 +1,13 @@
#ifndef __ARCH_MACH_COMMON_H
#define __ARCH_MACH_COMMON_H
extern void shmobile_earlytimer_init(void);
extern struct sys_timer shmobile_timer;
extern void shmobile_setup_console(void);
extern void shmobile_secondary_vector(void);
extern int shmobile_platform_cpu_kill(unsigned int cpu);
struct clk;
extern int clk_init(void);
extern int shmobile_clk_init(void);
extern void shmobile_handle_irq_intc(struct pt_regs *);
extern struct platform_suspend_ops shmobile_suspend_ops;
struct cpuidle_driver;
@ -14,6 +15,7 @@ extern void (*shmobile_cpuidle_modes[])(void);
extern void (*shmobile_cpuidle_setup)(struct cpuidle_driver *drv);
extern void sh7367_init_irq(void);
extern void sh7367_map_io(void);
extern void sh7367_add_early_devices(void);
extern void sh7367_add_standard_devices(void);
extern void sh7367_clock_init(void);
@ -22,6 +24,7 @@ extern struct clk sh7367_extalb1_clk;
extern struct clk sh7367_extal2_clk;
extern void sh7377_init_irq(void);
extern void sh7377_map_io(void);
extern void sh7377_add_early_devices(void);
extern void sh7377_add_standard_devices(void);
extern void sh7377_clock_init(void);
@ -30,6 +33,7 @@ extern struct clk sh7377_extalc1_clk;
extern struct clk sh7377_extal2_clk;
extern void sh7372_init_irq(void);
extern void sh7372_map_io(void);
extern void sh7372_add_early_devices(void);
extern void sh7372_add_standard_devices(void);
extern void sh7372_clock_init(void);
@ -41,6 +45,7 @@ extern struct clk sh7372_extal1_clk;
extern struct clk sh7372_extal2_clk;
extern void sh73a0_init_irq(void);
extern void sh73a0_map_io(void);
extern void sh73a0_add_early_devices(void);
extern void sh73a0_add_standard_devices(void);
extern void sh73a0_clock_init(void);
@ -56,12 +61,14 @@ extern int sh73a0_boot_secondary(unsigned int cpu);
extern void sh73a0_smp_prepare_cpus(void);
extern void r8a7740_init_irq(void);
extern void r8a7740_map_io(void);
extern void r8a7740_add_early_devices(void);
extern void r8a7740_add_standard_devices(void);
extern void r8a7740_clock_init(u8 md_ck);
extern void r8a7740_pinmux_init(void);
extern void r8a7779_init_irq(void);
extern void r8a7779_map_io(void);
extern void r8a7779_add_early_devices(void);
extern void r8a7779_add_standard_devices(void);
extern void r8a7779_clock_init(void);

45
arch/arm/mach-shmobile/setup-r8a7740.c
View File

@ -25,8 +25,41 @@
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <mach/r8a7740.h>
#include <mach/common.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
static struct map_desc r8a7740_io_desc[] __initdata = {
/*
* for CPGA/INTC/PFC
* 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
*/
{
.virtual = 0xe6000000,
.pfn = __phys_to_pfn(0xe6000000),
.length = 160 << 20,
.type = MT_DEVICE_NONSHARED
},
#ifdef CONFIG_CACHE_L2X0
/*
* for l2x0_init()
* 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
*/
{
.virtual = 0xf0002000,
.pfn = __phys_to_pfn(0xf0100000),
.length = PAGE_SIZE,
.type = MT_DEVICE_NONSHARED
},
#endif
};
void __init r8a7740_map_io(void)
{
iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
}
/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = {
@ -345,8 +378,20 @@ void __init r8a7740_add_standard_devices(void)
ARRAY_SIZE(r8a7740_late_devices));
}
static void __init r8a7740_earlytimer_init(void)
{
r8a7740_clock_init(0);
shmobile_earlytimer_init();
}
void __init r8a7740_add_early_devices(void)
{
early_platform_add_devices(r8a7740_early_devices,
ARRAY_SIZE(r8a7740_early_devices));
/* setup early console here as well */
shmobile_setup_console();
/* override timer setup with soc-specific code */
shmobile_timer.init = r8a7740_earlytimer_init;
}

54
arch/arm/mach-shmobile/setup-r8a7779.c
View File

@ -33,6 +33,31 @@
#include <mach/common.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <asm/hardware/cache-l2x0.h>
static struct map_desc r8a7779_io_desc[] __initdata = {
/* 2M entity map for 0xf0000000 (MPCORE) */
{
.virtual = 0xf0000000,
.pfn = __phys_to_pfn(0xf0000000),
.length = SZ_2M,
.type = MT_DEVICE_NONSHARED
},
/* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
{
.virtual = 0xfe000000,
.pfn = __phys_to_pfn(0xfe000000),
.length = SZ_16M,
.type = MT_DEVICE_NONSHARED
},
};
void __init r8a7779_map_io(void)
{
iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
}
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xffe40000,
@ -219,6 +244,10 @@ static struct platform_device *r8a7779_late_devices[] __initdata = {
void __init r8a7779_add_standard_devices(void)
{
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 64K*16way */
l2x0_init((void __iomem __force *)(0xf0100000), 0x40470000, 0x82000fff);
#endif
r8a7779_pm_init();
r8a7779_init_pm_domain(&r8a7779_sh4a);
@ -232,8 +261,33 @@ void __init r8a7779_add_standard_devices(void)
ARRAY_SIZE(r8a7779_late_devices));
}
static void __init r8a7779_earlytimer_init(void)
{
r8a7779_clock_init();
shmobile_earlytimer_init();
}
void __init r8a7779_add_early_devices(void)
{
early_platform_add_devices(r8a7779_early_devices,
ARRAY_SIZE(r8a7779_early_devices));
/* Early serial console setup is not included here due to
* memory map collisions. The SCIF serial ports in r8a7779
* are difficult to entity map 1:1 due to collision with the
* virtual memory range used by the coherent DMA code on ARM.
*
* Anyone wanting to debug early can remove UPF_IOREMAP from
* the sh-sci serial console platform data, adjust mapbase
* to a static M:N virt:phys mapping that needs to be added to
* the mappings passed with iotable_init() above.
*
* Then add a call to shmobile_setup_console() from this function.
*
* As a final step pass earlyprint=sh-sci.2,115200 on the kernel
* command line in case of the marzen board.
*/
/* override timer setup with soc-specific code */
shmobile_timer.init = r8a7779_earlytimer_init;
}

32
arch/arm/mach-shmobile/setup-sh7367.c
View File

@ -29,8 +29,28 @@
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
static struct map_desc sh7367_io_desc[] __initdata = {
/* create a 1:1 entity map for 0xe6xxxxxx
* used by CPGA, INTC and PFC.
*/
{
.virtual = 0xe6000000,
.pfn = __phys_to_pfn(0xe6000000),
.length = 256 << 20,
.type = MT_DEVICE_NONSHARED
},
};
void __init sh7367_map_io(void)
{
iotable_init(sh7367_io_desc, ARRAY_SIZE(sh7367_io_desc));
}
/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = {
@ -435,6 +455,12 @@ void __init sh7367_add_standard_devices(void)
ARRAY_SIZE(sh7367_devices));
}
static void __init sh7367_earlytimer_init(void)
{
sh7367_clock_init();
shmobile_earlytimer_init();
}
#define SYMSTPCR2 0xe6158048
#define SYMSTPCR2_CMT1 (1 << 29)
@ -445,4 +471,10 @@ void __init sh7367_add_early_devices(void)
early_platform_add_devices(sh7367_early_devices,
ARRAY_SIZE(sh7367_early_devices));
/* setup early console here as well */
shmobile_setup_console();
/* override timer setup with soc-specific code */
shmobile_timer.init = sh7367_earlytimer_init;
}

32
arch/arm/mach-shmobile/setup-sh7372.c
View File

@ -33,8 +33,28 @@
#include <linux/pm_domain.h>
#include <mach/hardware.h>
#include <mach/sh7372.h>
#include <mach/common.h>
#include <asm/mach/map.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
static struct map_desc sh7372_io_desc[] __initdata = {
/* create a 1:1 entity map for 0xe6xxxxxx
* used by CPGA, INTC and PFC.
*/
{
.virtual = 0xe6000000,
.pfn = __phys_to_pfn(0xe6000000),
.length = 256 << 20,
.type = MT_DEVICE_NONSHARED
},
};
void __init sh7372_map_io(void)
{
iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
}
/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = {
@ -1045,8 +1065,20 @@ void __init sh7372_add_standard_devices(void)
sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
}
static void __init sh7372_earlytimer_init(void)
{
sh7372_clock_init();
shmobile_earlytimer_init();
}
void __init sh7372_add_early_devices(void)
{
early_platform_add_devices(sh7372_early_devices,
ARRAY_SIZE(sh7372_early_devices));
/* setup early console here as well */
shmobile_setup_console();
/* override timer setup with soc-specific code */
shmobile_timer.init = sh7372_earlytimer_init;
}

32
arch/arm/mach-shmobile/setup-sh7377.c
View File

@ -30,8 +30,28 @@
#include <linux/sh_intc.h>
#include <linux/sh_timer.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <asm/mach/map.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
static struct map_desc sh7377_io_desc[] __initdata = {
/* create a 1:1 entity map for 0xe6xxxxxx
* used by CPGA, INTC and PFC.
*/
{
.virtual = 0xe6000000,
.pfn = __phys_to_pfn(0xe6000000),
.length = 256 << 20,
.type = MT_DEVICE_NONSHARED
},
};
void __init sh7377_map_io(void)
{
iotable_init(sh7377_io_desc, ARRAY_SIZE(sh7377_io_desc));
}
/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = {
@ -456,6 +476,12 @@ void __init sh7377_add_standard_devices(void)
ARRAY_SIZE(sh7377_devices));
}
static void __init sh7377_earlytimer_init(void)
{
sh7377_clock_init();
shmobile_earlytimer_init();
}
#define SMSTPCR3 0xe615013c
#define SMSTPCR3_CMT1 (1 << 29)
@ -466,4 +492,10 @@ void __init sh7377_add_early_devices(void)
early_platform_add_devices(sh7377_early_devices,
ARRAY_SIZE(sh7377_early_devices));
/* setup early console here as well */
shmobile_setup_console();
/* override timer setup with soc-specific code */
shmobile_timer.init = sh7377_earlytimer_init;
}

32
arch/arm/mach-shmobile/setup-sh73a0.c
View File

@ -32,8 +32,28 @@
#include <linux/sh_timer.h>
#include <mach/hardware.h>
#include <mach/sh73a0.h>
#include <mach/common.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
static struct map_desc sh73a0_io_desc[] __initdata = {
/* create a 1:1 entity map for 0xe6xxxxxx
* used by CPGA, INTC and PFC.
*/
{
.virtual = 0xe6000000,
.pfn = __phys_to_pfn(0xe6000000),
.length = 256 << 20,
.type = MT_DEVICE_NONSHARED
},
};
void __init sh73a0_map_io(void)
{
iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
}
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xe6c40000,
@ -667,8 +687,20 @@ void __init sh73a0_add_standard_devices(void)
ARRAY_SIZE(sh73a0_late_devices));
}
static void __init sh73a0_earlytimer_init(void)
{
sh73a0_clock_init();
shmobile_earlytimer_init();
}
void __init sh73a0_add_early_devices(void)
{
early_platform_add_devices(sh73a0_early_devices,
ARRAY_SIZE(sh73a0_early_devices));
/* setup early console here as well */
shmobile_setup_console();
/* override timer setup with soc-specific code */
shmobile_timer.init = sh73a0_earlytimer_init;
}

6
arch/arm/mach-shmobile/timer.c
View File

@ -36,11 +36,15 @@ static void __init shmobile_late_time_init(void)
early_platform_driver_probe("earlytimer", 2, 0);
}
static void __init shmobile_timer_init(void)
void __init shmobile_earlytimer_init(void)
{
late_time_init = shmobile_late_time_init;
}
static void __init shmobile_timer_init(void)
{
}
struct sys_timer shmobile_timer = {
.init = shmobile_timer_init,
};

2
arch/arm/mach-ux500/Kconfig
View File

@ -5,7 +5,7 @@ config UX500_SOC_COMMON
default y
select ARM_GIC
select HAS_MTU
select ARM_ERRATA_753970
select PL310_ERRATA_753970
select ARM_ERRATA_754322
select ARM_ERRATA_764369

2
arch/arm/mach-vexpress/Kconfig
View File

@ -7,7 +7,7 @@ config ARCH_VEXPRESS_CA9X4
select ARM_GIC
select ARM_ERRATA_720789
select ARM_ERRATA_751472
select ARM_ERRATA_753970
select PL310_ERRATA_753970
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0

4
arch/arm/mm/proc-v7.S
View File

@ -230,9 +230,7 @@ __v7_setup:
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_743622
teq r6, #0x20 @ present in r2p0
teqne r6, #0x21 @ present in r2p1
teqne r6, #0x22 @ present in r2p2
teq r5, #0x00200000 @ only present in r2p*
mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
orreq r10, r10, #1 << 6 @ set bit #6
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register

10
arch/arm/plat-omap/include/plat/irqs.h
View File

@ -428,8 +428,16 @@
#define OMAP_GPMC_NR_IRQS 8
#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
/* PRCM IRQ handler */
#ifdef CONFIG_ARCH_OMAP2PLUS
#define OMAP_PRCM_IRQ_BASE (OMAP_GPMC_IRQ_END)
#define OMAP_PRCM_NR_IRQS 64
#define OMAP_PRCM_IRQ_END (OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
#else
#define OMAP_PRCM_IRQ_END OMAP_GPMC_IRQ_END
#endif
#define NR_IRQS OMAP_GPMC_IRQ_END
#define NR_IRQS OMAP_PRCM_IRQ_END
#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))

2
arch/arm/plat-s3c24xx/dma.c
View File

@ -1249,7 +1249,7 @@ static void s3c2410_dma_resume(void)
struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1;
int channel;
for (channel = dma_channels - 1; channel >= 0; cp++, channel--)
for (channel = dma_channels - 1; channel >= 0; cp--, channel--)
s3c2410_dma_resume_chan(cp);
}

2
arch/arm/plat-samsung/devs.c
View File

@ -1456,7 +1456,7 @@ void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
#ifdef CONFIG_S3C_DEV_USB_HSOTG
static struct resource s3c_usb_hsotg_resources[] = {
[0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_16K),
[0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_128K),
[1] = DEFINE_RES_IRQ(IRQ_OTG),
};

6
arch/arm/plat-spear/time.c
View File

@ -145,11 +145,13 @@ static void clockevent_set_mode(enum clock_event_mode mode,
static int clockevent_next_event(unsigned long cycles,
struct clock_event_device *clk_event_dev)
{
u16 val;
u16 val = readw(gpt_base + CR(CLKEVT));
if (val & CTRL_ENABLE)
writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));
writew(cycles, gpt_base + LOAD(CLKEVT));
val = readw(gpt_base + CR(CLKEVT));
val |= CTRL_ENABLE | CTRL_INT_ENABLE;
writew(val, gpt_base + CR(CLKEVT));

4
arch/c6x/include/asm/processor.h
View File

@ -122,8 +122,8 @@ extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
extern unsigned long get_wchan(struct task_struct *p);
#define KSTK_EIP(tsk) (task_pt_regs(task)->pc)
#define KSTK_ESP(tsk) (task_pt_regs(task)->sp)
#define KSTK_EIP(task) (task_pt_regs(task)->pc)
#define KSTK_ESP(task) (task_pt_regs(task)->sp)
#define cpu_relax() do { } while (0)

2
arch/mips/alchemy/common/time.c
View File

@ -146,7 +146,7 @@ static int __init alchemy_time_init(unsigned int m2int)
cd->shift = 32;
cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */
cd->min_delta_ns = clockevent_delta2ns(9, cd); /* ~0.28ms */
clockevents_register_device(cd);
setup_irq(m2int, &au1x_rtcmatch2_irqaction);

2
arch/mips/ath79/dev-wmac.c
View File

@ -96,7 +96,7 @@ void __init ath79_register_wmac(u8 *cal_data)
{
if (soc_is_ar913x())
ar913x_wmac_setup();
if (soc_is_ar933x())
else if (soc_is_ar933x())
ar933x_wmac_setup();
else
BUG();

4
arch/mips/configs/nlm_xlp_defconfig
View File

@ -8,7 +8,7 @@ CONFIG_HIGH_RES_TIMERS=y
# CONFIG_SECCOMP is not set
CONFIG_USE_OF=y
CONFIG_EXPERIMENTAL=y
CONFIG_CROSS_COMPILE="mips-linux-gnu-"
CONFIG_CROSS_COMPILE=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
@ -22,7 +22,7 @@ CONFIG_AUDIT=y
CONFIG_CGROUPS=y
CONFIG_NAMESPACES=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlp"
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_INITRAMFS_COMPRESSION_LZMA=y

4
arch/mips/configs/nlm_xlr_defconfig
View File

@ -8,7 +8,7 @@ CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_KEXEC=y
CONFIG_EXPERIMENTAL=y
CONFIG_CROSS_COMPILE="mips-linux-gnu-"
CONFIG_CROSS_COMPILE=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
@ -22,7 +22,7 @@ CONFIG_AUDIT=y
CONFIG_NAMESPACES=y
CONFIG_SCHED_AUTOGROUP=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlr"
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_INITRAMFS_COMPRESSION_GZIP=y

2
arch/mips/configs/powertv_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_HZ_1000=y
CONFIG_PREEMPT=y
# CONFIG_SECCOMP is not set
CONFIG_EXPERIMENTAL=y
CONFIG_CROSS_COMPILE="mips-linux-"
CONFIG_CROSS_COMPILE=""
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=16

20
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
View File

@ -11,6 +11,9 @@
#include <asm/io.h>
#include <asm/mach-au1x00/au1000.h>
struct gpio;
struct gpio_chip;
/* with the current GPIC design, up to 128 GPIOs are possible.
* The only implementation so far is in the Au1300, which has 75 externally
* available GPIOs.
@ -203,7 +206,22 @@ static inline int gpio_request(unsigned int gpio, const char *label)
return 0;
}
static inline void gpio_free(unsigned int gpio)
static inline int gpio_request_one(unsigned gpio,
unsigned long flags, const char *label)
{
return 0;
}
static inline int gpio_request_array(struct gpio *array, size_t num)
{
return 0;
}
static inline void gpio_free(unsigned gpio)
{
}
static inline void gpio_free_array(struct gpio *array, size_t num)
{
}

3
arch/mips/include/asm/page.h
View File

@ -39,9 +39,6 @@
#define HPAGE_MASK (~(HPAGE_SIZE - 1))
#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
#else /* !CONFIG_HUGETLB_PAGE */
# ifndef BUILD_BUG
# define BUILD_BUG() do { extern void __build_bug(void); __build_bug(); } while (0)
# endif
#define HPAGE_SHIFT ({BUILD_BUG(); 0; })
#define HPAGE_SIZE ({BUILD_BUG(); 0; })
#define HPAGE_MASK ({BUILD_BUG(); 0; })

1
arch/mips/kernel/smp-bmips.c
View File

@ -8,7 +8,6 @@
* SMP support for BMIPS
*/
#include <linux/version.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/mm.h>

2
arch/mips/kernel/traps.c
View File

@ -1135,7 +1135,7 @@ asmlinkage void do_mt(struct pt_regs *regs)
printk(KERN_DEBUG "YIELD Scheduler Exception\n");
break;
case 5:
printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
break;
default:
printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",

1
arch/mips/kernel/vmlinux.lds.S
View File

@ -69,7 +69,6 @@ SECTIONS
RODATA
/* writeable */
_sdata = .; /* Start of data section */
.data : { /* Data */
. = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */

36
arch/mips/mm/fault.c
View File

@ -42,6 +42,8 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long writ
const int field = sizeof(unsigned long) * 2;
siginfo_t info;
int fault;
unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE |
(write ? FAULT_FLAG_WRITE : 0);
#if 0
printk("Cpu%d[%s:%d:%0*lx:%ld:%0*lx]\n", raw_smp_processor_id(),
@ -91,6 +93,7 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long writ
if (in_atomic() || !mm)
goto bad_area_nosemaphore;
retry:
down_read(&mm->mmap_sem);
vma = find_vma(mm, address);
if (!vma)
@ -144,7 +147,11 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long writ
* make sure we exit gracefully rather than endlessly redo
* the fault.
*/
fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0);
fault = handle_mm_fault(mm, vma, address, flags);
if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
return;
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
if (unlikely(fault & VM_FAULT_ERROR)) {
if (fault & VM_FAULT_OOM)
@ -153,12 +160,27 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long writ
goto do_sigbus;
BUG();
}
if (fault & VM_FAULT_MAJOR) {
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, address);
tsk->maj_flt++;
} else {
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, address);
tsk->min_flt++;
if (flags & FAULT_FLAG_ALLOW_RETRY) {
if (fault & VM_FAULT_MAJOR) {
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
regs, address);
tsk->maj_flt++;
} else {
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1,
regs, address);
tsk->min_flt++;
}
if (fault & VM_FAULT_RETRY) {
flags &= ~FAULT_FLAG_ALLOW_RETRY;
/*
* No need to up_read(&mm->mmap_sem) as we would
* have already released it in __lock_page_or_retry
* in mm/filemap.c.
*/
goto retry;
}
}
up_read(&mm->mmap_sem);

5
arch/mips/pci/pci.c
View File

@ -279,7 +279,6 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
{
/* Propagate hose info into the subordinate devices. */
struct list_head *ln;
struct pci_dev *dev = bus->self;
if (pci_probe_only && dev &&
@ -288,9 +287,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
pcibios_fixup_device_resources(dev, bus);
}
for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
dev = pci_dev_b(ln);
list_for_each_entry(dev, &bus->devices, bus_list) {
if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
pcibios_fixup_device_resources(dev, bus);
}

10
arch/mips/pmc-sierra/yosemite/ht-irq.c
View File

@ -35,16 +35,6 @@
*/
void __init titan_ht_pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_bus *current_bus = bus;
struct pci_dev *devices;
struct list_head *devices_link;
list_for_each(devices_link, &(current_bus->devices)) {
devices = pci_dev_b(devices_link);
if (devices == NULL)
continue;
}
/*
* PLX and SPKT related changes go here
*/

2
arch/mips/txx9/generic/7segled.c
View File

@ -102,7 +102,7 @@ static int __init tx_7segled_init_sysfs(void)
break;
}
dev->id = i;
dev->dev = &tx_7segled_subsys;
dev->bus = &tx_7segled_subsys;
error = device_register(dev);
if (!error) {
device_create_file(dev, &dev_attr_ascii);

2
arch/sh/boards/mach-highlander/setup.c
View File

@ -322,7 +322,7 @@ static void ivdr_clk_disable(struct clk *clk)
__raw_writew(__raw_readw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL);
}
static struct clk_ops ivdr_clk_ops = {
static struct sh_clk_ops ivdr_clk_ops = {
.enable = ivdr_clk_enable,
.disable = ivdr_clk_disable,
};

2
arch/sh/boards/mach-sdk7786/setup.c
View File

@ -167,7 +167,7 @@ static void sdk7786_pcie_clk_disable(struct clk *clk)
fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR);
}
static struct clk_ops sdk7786_pcie_clk_ops = {
static struct sh_clk_ops sdk7786_pcie_clk_ops = {
.enable = sdk7786_pcie_clk_enable,
.disable = sdk7786_pcie_clk_disable,
};

2
arch/sh/include/asm/clock.h
View File

@ -4,7 +4,7 @@
#include <linux/sh_clk.h>
/* Should be defined by processor-specific code */
void __deprecated arch_init_clk_ops(struct clk_ops **, int type);
void __deprecated arch_init_clk_ops(struct sh_clk_ops **, int type);
int __init arch_clk_init(void);
/* arch/sh/kernel/cpu/clock-cpg.c */

12
arch/sh/kernel/cpu/sh2/clock-sh7619.c
View File

@ -28,7 +28,7 @@ static void master_clk_init(struct clk *clk)
clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
}
static struct clk_ops sh7619_master_clk_ops = {
static struct sh_clk_ops sh7619_master_clk_ops = {
.init = master_clk_init,
};
@ -38,7 +38,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7619_module_clk_ops = {
static struct sh_clk_ops sh7619_module_clk_ops = {
.recalc = module_clk_recalc,
};
@ -47,22 +47,22 @@ static unsigned long bus_clk_recalc(struct clk *clk)
return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
}
static struct clk_ops sh7619_bus_clk_ops = {
static struct sh_clk_ops sh7619_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
static struct clk_ops sh7619_cpu_clk_ops = {
static struct sh_clk_ops sh7619_cpu_clk_ops = {
.recalc = followparent_recalc,
};
static struct clk_ops *sh7619_clk_ops[] = {
static struct sh_clk_ops *sh7619_clk_ops[] = {
&sh7619_master_clk_ops,
&sh7619_module_clk_ops,
&sh7619_bus_clk_ops,
&sh7619_cpu_clk_ops,
};
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
{
if (test_mode_pin(MODE_PIN2 | MODE_PIN0) ||
test_mode_pin(MODE_PIN2 | MODE_PIN1))

12
arch/sh/kernel/cpu/sh2a/clock-sh7201.c
View File

@ -30,7 +30,7 @@ static void master_clk_init(struct clk *clk)
pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
}
static struct clk_ops sh7201_master_clk_ops = {
static struct sh_clk_ops sh7201_master_clk_ops = {
.init = master_clk_init,
};
@ -40,7 +40,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7201_module_clk_ops = {
static struct sh_clk_ops sh7201_module_clk_ops = {
.recalc = module_clk_recalc,
};
@ -50,7 +50,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7201_bus_clk_ops = {
static struct sh_clk_ops sh7201_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
@ -60,18 +60,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7201_cpu_clk_ops = {
static struct sh_clk_ops sh7201_cpu_clk_ops = {
.recalc = cpu_clk_recalc,
};
static struct clk_ops *sh7201_clk_ops[] = {
static struct sh_clk_ops *sh7201_clk_ops[] = {
&sh7201_master_clk_ops,
&sh7201_module_clk_ops,
&sh7201_bus_clk_ops,
&sh7201_cpu_clk_ops,
};
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
{
if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
pll2_mult = 1;

12
arch/sh/kernel/cpu/sh2a/clock-sh7203.c
View File

@ -32,7 +32,7 @@ static void master_clk_init(struct clk *clk)
clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
}
static struct clk_ops sh7203_master_clk_ops = {
static struct sh_clk_ops sh7203_master_clk_ops = {
.init = master_clk_init,
};
@ -42,7 +42,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7203_module_clk_ops = {
static struct sh_clk_ops sh7203_module_clk_ops = {
.recalc = module_clk_recalc,
};
@ -52,22 +52,22 @@ static unsigned long bus_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx-2];
}
static struct clk_ops sh7203_bus_clk_ops = {
static struct sh_clk_ops sh7203_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
static struct clk_ops sh7203_cpu_clk_ops = {
static struct sh_clk_ops sh7203_cpu_clk_ops = {
.recalc = followparent_recalc,
};
static struct clk_ops *sh7203_clk_ops[] = {
static struct sh_clk_ops *sh7203_clk_ops[] = {
&sh7203_master_clk_ops,
&sh7203_module_clk_ops,
&sh7203_bus_clk_ops,
&sh7203_cpu_clk_ops,
};
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
{
if (test_mode_pin(MODE_PIN1))
pll2_mult = 4;

12
arch/sh/kernel/cpu/sh2a/clock-sh7206.c
View File

@ -29,7 +29,7 @@ static void master_clk_init(struct clk *clk)
clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
}
static struct clk_ops sh7206_master_clk_ops = {
static struct sh_clk_ops sh7206_master_clk_ops = {
.init = master_clk_init,
};
@ -39,7 +39,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7206_module_clk_ops = {
static struct sh_clk_ops sh7206_module_clk_ops = {
.recalc = module_clk_recalc,
};
@ -48,7 +48,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
}
static struct clk_ops sh7206_bus_clk_ops = {
static struct sh_clk_ops sh7206_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
@ -58,18 +58,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7206_cpu_clk_ops = {
static struct sh_clk_ops sh7206_cpu_clk_ops = {
.recalc = cpu_clk_recalc,
};
static struct clk_ops *sh7206_clk_ops[] = {
static struct sh_clk_ops *sh7206_clk_ops[] = {
&sh7206_master_clk_ops,
&sh7206_module_clk_ops,
&sh7206_bus_clk_ops,
&sh7206_cpu_clk_ops,
};
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
{
if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
pll2_mult = 1;

12
arch/sh/kernel/cpu/sh3/clock-sh3.c
View File

@ -34,7 +34,7 @@ static void master_clk_init(struct clk *clk)
clk->rate *= pfc_divisors[idx];
}
static struct clk_ops sh3_master_clk_ops = {
static struct sh_clk_ops sh3_master_clk_ops = {
.init = master_clk_init,
};
@ -46,7 +46,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh3_module_clk_ops = {
static struct sh_clk_ops sh3_module_clk_ops = {
.recalc = module_clk_recalc,
};
@ -58,7 +58,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
return clk->parent->rate / stc_multipliers[idx];
}
static struct clk_ops sh3_bus_clk_ops = {
static struct sh_clk_ops sh3_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
@ -70,18 +70,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh3_cpu_clk_ops = {
static struct sh_clk_ops sh3_cpu_clk_ops = {
.recalc = cpu_clk_recalc,
};
static struct clk_ops *sh3_clk_ops[] = {
static struct sh_clk_ops *sh3_clk_ops[] = {
&sh3_master_clk_ops,
&sh3_module_clk_ops,
&sh3_bus_clk_ops,
&sh3_cpu_clk_ops,
};
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
{
if (idx < ARRAY_SIZE(sh3_clk_ops))
*ops = sh3_clk_ops[idx];

12
arch/sh/kernel/cpu/sh3/clock-sh7705.c
View File

@ -35,7 +35,7 @@ static void master_clk_init(struct clk *clk)
clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003];
}
static struct clk_ops sh7705_master_clk_ops = {
static struct sh_clk_ops sh7705_master_clk_ops = {
.init = master_clk_init,
};
@ -45,7 +45,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7705_module_clk_ops = {
static struct sh_clk_ops sh7705_module_clk_ops = {
.recalc = module_clk_recalc,
};
@ -55,7 +55,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
return clk->parent->rate / stc_multipliers[idx];
}
static struct clk_ops sh7705_bus_clk_ops = {
static struct sh_clk_ops sh7705_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
@ -65,18 +65,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7705_cpu_clk_ops = {
static struct sh_clk_ops sh7705_cpu_clk_ops = {
.recalc = cpu_clk_recalc,
};
static struct clk_ops *sh7705_clk_ops[] = {
static struct sh_clk_ops *sh7705_clk_ops[] = {
&sh7705_master_clk_ops,
&sh7705_module_clk_ops,
&sh7705_bus_clk_ops,
&sh7705_cpu_clk_ops,
};
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
{
if (idx < ARRAY_SIZE(sh7705_clk_ops))
*ops = sh7705_clk_ops[idx];

12
arch/sh/kernel/cpu/sh3/clock-sh7706.c
View File

@ -30,7 +30,7 @@ static void master_clk_init(struct clk *clk)
clk->rate *= pfc_divisors[idx];
}
static struct clk_ops sh7706_master_clk_ops = {
static struct sh_clk_ops sh7706_master_clk_ops = {
.init = master_clk_init,
};
@ -42,7 +42,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7706_module_clk_ops = {
static struct sh_clk_ops sh7706_module_clk_ops = {
.recalc = module_clk_recalc,
};
@ -54,7 +54,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
return clk->parent->rate / stc_multipliers[idx];
}
static struct clk_ops sh7706_bus_clk_ops = {
static struct sh_clk_ops sh7706_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
@ -66,18 +66,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7706_cpu_clk_ops = {
static struct sh_clk_ops sh7706_cpu_clk_ops = {
.recalc = cpu_clk_recalc,
};
static struct clk_ops *sh7706_clk_ops[] = {
static struct sh_clk_ops *sh7706_clk_ops[] = {
&sh7706_master_clk_ops,
&sh7706_module_clk_ops,
&sh7706_bus_clk_ops,
&sh7706_cpu_clk_ops,
};
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
{
if (idx < ARRAY_SIZE(sh7706_clk_ops))
*ops = sh7706_clk_ops[idx];

12
arch/sh/kernel/cpu/sh3/clock-sh7709.c
View File

@ -30,7 +30,7 @@ static void master_clk_init(struct clk *clk)
clk->rate *= pfc_divisors[idx];
}
static struct clk_ops sh7709_master_clk_ops = {
static struct sh_clk_ops sh7709_master_clk_ops = {
.init = master_clk_init,
};
@ -42,7 +42,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7709_module_clk_ops = {
static struct sh_clk_ops sh7709_module_clk_ops = {
.recalc = module_clk_recalc,
};
@ -55,7 +55,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
return clk->parent->rate * stc_multipliers[idx];
}
static struct clk_ops sh7709_bus_clk_ops = {
static struct sh_clk_ops sh7709_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
@ -67,18 +67,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7709_cpu_clk_ops = {
static struct sh_clk_ops sh7709_cpu_clk_ops = {
.recalc = cpu_clk_recalc,
};
static struct clk_ops *sh7709_clk_ops[] = {
static struct sh_clk_ops *sh7709_clk_ops[] = {
&sh7709_master_clk_ops,
&sh7709_module_clk_ops,
&sh7709_bus_clk_ops,
&sh7709_cpu_clk_ops,
};
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
{
if (idx < ARRAY_SIZE(sh7709_clk_ops))
*ops = sh7709_clk_ops[idx];

12
arch/sh/kernel/cpu/sh3/clock-sh7710.c
View File

@ -29,7 +29,7 @@ static void master_clk_init(struct clk *clk)
clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007];
}
static struct clk_ops sh7710_master_clk_ops = {
static struct sh_clk_ops sh7710_master_clk_ops = {
.init = master_clk_init,
};
@ -39,7 +39,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
return clk->parent->rate / md_table[idx];
}
static struct clk_ops sh7710_module_clk_ops = {
static struct sh_clk_ops sh7710_module_clk_ops = {
.recalc = module_clk_recalc,
};
@ -49,7 +49,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
return clk->parent->rate / md_table[idx];
}
static struct clk_ops sh7710_bus_clk_ops = {
static struct sh_clk_ops sh7710_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
@ -59,18 +59,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
return clk->parent->rate / md_table[idx];
}
static struct clk_ops sh7710_cpu_clk_ops = {
static struct sh_clk_ops sh7710_cpu_clk_ops = {
.recalc = cpu_clk_recalc,
};
static struct clk_ops *sh7710_clk_ops[] = {
static struct sh_clk_ops *sh7710_clk_ops[] = {
&sh7710_master_clk_ops,
&sh7710_module_clk_ops,
&sh7710_bus_clk_ops,
&sh7710_cpu_clk_ops,
};
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
{
if (idx < ARRAY_SIZE(sh7710_clk_ops))
*ops = sh7710_clk_ops[idx];

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