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drm/i915: Make all GPU resets atomic
In preparation for the next few commits, make resetting the GPU atomic. Currently, we have prepared gen6+ for atomic resetting of individual engines, but now there is a requirement to perform the whole device level reset (just the register poking) from inside an atomic context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190125132230.22221-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
832a67bdb2
commit
ade8a0f598
@ -12,6 +12,8 @@
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#include "intel_guc.h"
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#define RESET_MAX_RETRIES 3
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static void engine_skip_context(struct i915_request *rq)
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{
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struct intel_engine_cs *engine = rq->engine;
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@ -144,14 +146,14 @@ static int i915_do_reset(struct drm_i915_private *i915,
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/* Assert reset for at least 20 usec, and wait for acknowledgement. */
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pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
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usleep_range(50, 200);
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err = wait_for(i915_in_reset(pdev), 500);
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udelay(50);
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err = wait_for_atomic(i915_in_reset(pdev), 50);
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/* Clear the reset request. */
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pci_write_config_byte(pdev, I915_GDRST, 0);
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usleep_range(50, 200);
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udelay(50);
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if (!err)
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err = wait_for(!i915_in_reset(pdev), 500);
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err = wait_for_atomic(!i915_in_reset(pdev), 50);
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return err;
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}
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@ -171,7 +173,7 @@ static int g33_do_reset(struct drm_i915_private *i915,
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struct pci_dev *pdev = i915->drm.pdev;
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pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
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return wait_for(g4x_reset_complete(pdev), 500);
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return wait_for_atomic(g4x_reset_complete(pdev), 50);
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}
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static int g4x_do_reset(struct drm_i915_private *dev_priv,
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@ -182,13 +184,13 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
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int ret;
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/* WaVcpClkGateDisableForMediaReset:ctg,elk */
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I915_WRITE(VDECCLK_GATE_D,
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I915_WRITE_FW(VDECCLK_GATE_D,
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I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
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POSTING_READ(VDECCLK_GATE_D);
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POSTING_READ_FW(VDECCLK_GATE_D);
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pci_write_config_byte(pdev, I915_GDRST,
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GRDOM_MEDIA | GRDOM_RESET_ENABLE);
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ret = wait_for(g4x_reset_complete(pdev), 500);
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ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
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if (ret) {
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DRM_DEBUG_DRIVER("Wait for media reset failed\n");
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goto out;
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@ -196,7 +198,7 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
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pci_write_config_byte(pdev, I915_GDRST,
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GRDOM_RENDER | GRDOM_RESET_ENABLE);
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ret = wait_for(g4x_reset_complete(pdev), 500);
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ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
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if (ret) {
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DRM_DEBUG_DRIVER("Wait for render reset failed\n");
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goto out;
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@ -205,9 +207,9 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
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out:
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pci_write_config_byte(pdev, I915_GDRST, 0);
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I915_WRITE(VDECCLK_GATE_D,
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I915_WRITE_FW(VDECCLK_GATE_D,
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I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
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POSTING_READ(VDECCLK_GATE_D);
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POSTING_READ_FW(VDECCLK_GATE_D);
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return ret;
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}
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@ -218,27 +220,29 @@ static int ironlake_do_reset(struct drm_i915_private *dev_priv,
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{
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int ret;
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I915_WRITE(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
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ret = intel_wait_for_register(dev_priv,
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ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
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500);
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I915_WRITE_FW(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
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ret = __intel_wait_for_register_fw(dev_priv, ILK_GDSR,
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ILK_GRDOM_RESET_ENABLE, 0,
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5000, 0,
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NULL);
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if (ret) {
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DRM_DEBUG_DRIVER("Wait for render reset failed\n");
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goto out;
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}
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I915_WRITE(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
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ret = intel_wait_for_register(dev_priv,
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ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
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500);
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I915_WRITE_FW(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
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ret = __intel_wait_for_register_fw(dev_priv, ILK_GDSR,
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ILK_GRDOM_RESET_ENABLE, 0,
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5000, 0,
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NULL);
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if (ret) {
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DRM_DEBUG_DRIVER("Wait for media reset failed\n");
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goto out;
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}
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out:
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I915_WRITE(ILK_GDSR, 0);
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POSTING_READ(ILK_GDSR);
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I915_WRITE_FW(ILK_GDSR, 0);
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POSTING_READ_FW(ILK_GDSR);
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return ret;
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}
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@ -527,32 +531,21 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *i915)
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int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask)
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{
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reset_func reset = intel_get_gpu_reset(i915);
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const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
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reset_func reset;
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int ret = -ETIMEDOUT;
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int retry;
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int ret;
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/*
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* We want to perform per-engine reset from atomic context (e.g.
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* softirq), which imposes the constraint that we cannot sleep.
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* However, experience suggests that spending a bit of time waiting
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* for a reset helps in various cases, so for a full-device reset
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* we apply the opposite rule and wait if we want to. As we should
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* always follow up a failed per-engine reset with a full device reset,
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* being a little faster, stricter and more error prone for the
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* atomic case seems an acceptable compromise.
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*
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* Unfortunately this leads to a bimodal routine, when the goal was
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* to have a single reset function that worked for resetting any
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* number of engines simultaneously.
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*/
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might_sleep_if(engine_mask == ALL_ENGINES);
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reset = intel_get_gpu_reset(i915);
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if (!reset)
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return -ENODEV;
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/*
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* If the power well sleeps during the reset, the reset
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* request may be dropped and never completes (causing -EIO).
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*/
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intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
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for (retry = 0; retry < 3; retry++) {
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for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
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/*
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* We stop engines, otherwise we might get failed reset and a
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* dead gpu (on elk). Also as modern gpu as kbl can suffer
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@ -569,15 +562,10 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask)
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*/
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i915_stop_engines(i915, engine_mask);
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ret = -ENODEV;
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if (reset) {
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GEM_TRACE("engine_mask=%x\n", engine_mask);
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preempt_disable();
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ret = reset(i915, engine_mask, retry);
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}
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if (ret != -ETIMEDOUT || engine_mask != ALL_ENGINES)
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break;
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cond_resched();
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preempt_enable();
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}
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intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
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@ -1014,7 +1002,7 @@ void i915_reset(struct drm_i915_private *i915,
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goto error;
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}
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for (i = 0; i < 3; i++) {
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for (i = 0; i < RESET_MAX_RETRIES; i++) {
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ret = intel_gpu_reset(i915, ALL_ENGINES);
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if (ret == 0)
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break;
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