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dt-bindings: pwm: Add bindings doc for ZTE ZX PWM controller

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It adds bindings document for ZTE ZX PWM controller. The device has two
clocks: PCLK and WCLK. The PCLK is for register access, and WCLK is the
reference clock for calculating period and duty cycles. Also, the device
supports polarity configuration, so #pwm-cells should be 3.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Shawn Guo 2017-07-27 16:23:36 +08:00 committed by Thierry Reding
parent 8a88b2a201
commit acfc3e348c
1 changed files with 22 additions and 0 deletions
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Documentation/devicetree/bindings/pwm/pwm-zx.txt Normal file
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ZTE ZX PWM controller
Required properties:
- compatible: Should be "zte,zx296718-pwm".
- reg: Physical base address and length of the controller's registers.
- clocks : The phandle and specifier referencing the controller's clocks.
- clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The
PCLK is for register access, while WCLK is the reference clock for
calculating period and duty cycles.
- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
the cells format.
Example:
pwm: pwm@1439000 {
compatible = "zte,zx296718-pwm";
reg = <0x1439000 0x1000>;
clocks = <&lsp1crm LSP1_PWM_PCLK>,
<&lsp1crm LSP1_PWM_WCLK>;
clock-names = "pclk", "wclk";
#pwm-cells = <3>;
};