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ASoC: SOF: Intel: hda: Add helper function to program ICCMAX stream
For some platforms, the recommended HW sequence for FW boot involves starting a specially crafted capture stream before powering on the DSP cores. Add a helper function to define the minimal recommended stream programming sequence for this stream. Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://lore.kernel.org/r/20200826184532.1612070-4-ranjani.sridharan@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -23,6 +23,8 @@
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#include "../sof-audio.h"
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#include "../sof-audio.h"
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#include "hda.h"
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#include "hda.h"
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#define HDA_LTRP_GB_VALUE_US 95
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/*
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/*
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* set up one of BDL entries for a stream
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* set up one of BDL entries for a stream
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*/
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*/
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@ -322,6 +324,73 @@ int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
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return 0;
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return 0;
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}
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}
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/* minimal recommended programming for ICCMAX stream */
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int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream,
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struct snd_dma_buffer *dmab,
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struct snd_pcm_hw_params *params)
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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struct hdac_stream *hstream = &stream->hstream;
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int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
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int ret;
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u32 mask = 0x1 << hstream->index;
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if (!stream) {
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dev_err(sdev->dev, "error: no stream available\n");
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return -ENODEV;
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}
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if (hstream->posbuf)
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*hstream->posbuf = 0;
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/* reset BDL address */
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
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0x0);
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
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0x0);
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hstream->frags = 0;
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ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream);
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if (ret < 0) {
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dev_err(sdev->dev, "error: set up of BDL failed\n");
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return ret;
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}
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/* program BDL address */
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
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(u32)hstream->bdl.addr);
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
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upper_32_bits(hstream->bdl.addr));
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/* program cyclic buffer length */
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL,
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hstream->bufsize);
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/* program last valid index */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI,
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0xffff, (hstream->frags - 1));
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/* decouple host and link DMA, enable DSP features */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
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mask, mask);
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/* Follow HW recommendation to set the guardband value to 95us during FW boot */
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snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, HDA_LTRP_GB_VALUE_US);
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/* start DMA */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
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SOF_HDA_SD_CTL_DMA_START, SOF_HDA_SD_CTL_DMA_START);
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return 0;
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}
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/*
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/*
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* prepare for common hdac registers settings, for both code loader
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* prepare for common hdac registers settings, for both code loader
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* and normal stream.
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* and normal stream.
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@ -246,6 +246,7 @@
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/* Intel Vendor Specific Registers */
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/* Intel Vendor Specific Registers */
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#define HDA_VS_INTEL_EM2 0x1030
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#define HDA_VS_INTEL_EM2 0x1030
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#define HDA_VS_INTEL_EM2_L1SEN BIT(13)
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#define HDA_VS_INTEL_EM2_L1SEN BIT(13)
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#define HDA_VS_INTEL_LTRP_GB_MASK 0x3F
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/* HIPCI */
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/* HIPCI */
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#define HDA_DSP_REG_HIPCI_BUSY BIT(31)
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#define HDA_DSP_REG_HIPCI_BUSY BIT(31)
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@ -546,6 +547,9 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
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struct hdac_ext_stream *stream,
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struct hdac_ext_stream *stream,
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struct snd_dma_buffer *dmab,
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struct snd_dma_buffer *dmab,
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struct snd_pcm_hw_params *params);
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struct snd_pcm_hw_params *params);
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int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream,
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struct snd_dma_buffer *dmab,
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struct snd_pcm_hw_params *params);
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int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
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int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
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struct hdac_ext_stream *stream, int cmd);
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struct hdac_ext_stream *stream, int cmd);
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irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
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irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
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