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riscv/mm/fault: Move vmalloc fault handling to vmalloc_fault()
This patch moves the vmalloc fault handling in do_page_fault() to vmalloc_fault() function and converts gotos to calls to the new function. Signed-off-by: Pekka Enberg <penberg@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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a51271d99c
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@ -53,6 +53,84 @@ static inline void bad_area(struct pt_regs *regs, struct mm_struct *mm, int code
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no_context(regs, addr);
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}
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static void inline vmalloc_fault(struct pt_regs *regs, int code, unsigned long addr)
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{
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pgd_t *pgd, *pgd_k;
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pud_t *pud, *pud_k;
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p4d_t *p4d, *p4d_k;
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pmd_t *pmd, *pmd_k;
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pte_t *pte_k;
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int index;
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/* User mode accesses just cause a SIGSEGV */
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if (user_mode(regs))
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return do_trap(regs, SIGSEGV, code, addr);
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/*
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* Synchronize this task's top level page-table
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* with the 'reference' page table.
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*
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* Do _not_ use "tsk->active_mm->pgd" here.
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* We might be inside an interrupt in the middle
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* of a task switch.
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*/
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index = pgd_index(addr);
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pgd = (pgd_t *)pfn_to_virt(csr_read(CSR_SATP)) + index;
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pgd_k = init_mm.pgd + index;
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if (!pgd_present(*pgd_k)) {
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no_context(regs, addr);
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return;
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}
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set_pgd(pgd, *pgd_k);
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p4d = p4d_offset(pgd, addr);
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p4d_k = p4d_offset(pgd_k, addr);
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if (!p4d_present(*p4d_k)) {
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no_context(regs, addr);
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return;
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}
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pud = pud_offset(p4d, addr);
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pud_k = pud_offset(p4d_k, addr);
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if (!pud_present(*pud_k)) {
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no_context(regs, addr);
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return;
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}
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/*
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* Since the vmalloc area is global, it is unnecessary
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* to copy individual PTEs
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*/
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pmd = pmd_offset(pud, addr);
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pmd_k = pmd_offset(pud_k, addr);
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if (!pmd_present(*pmd_k)) {
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no_context(regs, addr);
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return;
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}
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set_pmd(pmd, *pmd_k);
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/*
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* Make sure the actual PTE exists as well to
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* catch kernel vmalloc-area accesses to non-mapped
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* addresses. If we don't do this, this will just
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* silently loop forever.
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*/
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pte_k = pte_offset_kernel(pmd_k, addr);
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if (!pte_present(*pte_k)) {
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no_context(regs, addr);
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return;
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}
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/*
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* The kernel assumes that TLBs don't cache invalid
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* entries, but in RISC-V, SFENCE.VMA specifies an
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* ordering constraint, not a cache flush; it is
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* necessary even after writing invalid entries.
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*/
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local_flush_tlb_page(addr);
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}
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/*
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* This routine handles page faults. It determines the address and the
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* problem, and then passes it off to one of the appropriate routines.
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@ -82,8 +160,10 @@ asmlinkage void do_page_fault(struct pt_regs *regs)
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* only copy the information from the master page table,
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* nothing more.
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*/
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if (unlikely((addr >= VMALLOC_START) && (addr <= VMALLOC_END)))
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goto vmalloc_fault;
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if (unlikely((addr >= VMALLOC_START) && (addr <= VMALLOC_END))) {
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vmalloc_fault(regs, code, addr);
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return;
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}
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/* Enable interrupts if they were enabled in the parent context. */
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if (likely(regs->status & SR_PIE))
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@ -211,84 +291,4 @@ asmlinkage void do_page_fault(struct pt_regs *regs)
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}
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do_trap(regs, SIGBUS, BUS_ADRERR, addr);
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return;
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vmalloc_fault:
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{
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pgd_t *pgd, *pgd_k;
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pud_t *pud, *pud_k;
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p4d_t *p4d, *p4d_k;
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pmd_t *pmd, *pmd_k;
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pte_t *pte_k;
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int index;
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/* User mode accesses just cause a SIGSEGV */
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if (user_mode(regs))
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return do_trap(regs, SIGSEGV, code, addr);
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/*
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* Synchronize this task's top level page-table
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* with the 'reference' page table.
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*
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* Do _not_ use "tsk->active_mm->pgd" here.
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* We might be inside an interrupt in the middle
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* of a task switch.
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*/
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index = pgd_index(addr);
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pgd = (pgd_t *)pfn_to_virt(csr_read(CSR_SATP)) + index;
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pgd_k = init_mm.pgd + index;
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if (!pgd_present(*pgd_k)) {
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no_context(regs, addr);
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return;
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}
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set_pgd(pgd, *pgd_k);
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p4d = p4d_offset(pgd, addr);
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p4d_k = p4d_offset(pgd_k, addr);
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if (!p4d_present(*p4d_k)) {
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no_context(regs, addr);
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return;
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}
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pud = pud_offset(p4d, addr);
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pud_k = pud_offset(p4d_k, addr);
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if (!pud_present(*pud_k)) {
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no_context(regs, addr);
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return;
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}
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/*
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* Since the vmalloc area is global, it is unnecessary
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* to copy individual PTEs
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*/
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pmd = pmd_offset(pud, addr);
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pmd_k = pmd_offset(pud_k, addr);
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if (!pmd_present(*pmd_k)) {
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no_context(regs, addr);
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return;
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}
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set_pmd(pmd, *pmd_k);
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/*
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* Make sure the actual PTE exists as well to
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* catch kernel vmalloc-area accesses to non-mapped
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* addresses. If we don't do this, this will just
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* silently loop forever.
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*/
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pte_k = pte_offset_kernel(pmd_k, addr);
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if (!pte_present(*pte_k)) {
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no_context(regs, addr);
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return;
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}
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/*
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* The kernel assumes that TLBs don't cache invalid
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* entries, but in RISC-V, SFENCE.VMA specifies an
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* ordering constraint, not a cache flush; it is
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* necessary even after writing invalid entries.
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*/
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local_flush_tlb_page(addr);
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return;
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}
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}
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