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drm/amd/display: Add DC interface for custom CSC matrix

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Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yue Hin Lau 2017-06-28 17:21:42 -04:00 committed by Alex Deucher
parent 1c604cd862
commit abe07e8083
8 changed files with 252 additions and 4 deletions
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26
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -221,6 +221,29 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream)
return ret;
}
static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream)
{
struct core_dc *core_dc = DC_TO_CORE(dc);
struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
int i = 0;
bool ret = false;
struct pipe_ctx *pipes;
for (i = 0; i < MAX_PIPES; i++) {
if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
== core_stream) {
pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
core_dc->hwss.program_csc_matrix(pipes,
core_stream->public.output_color_space,
core_stream->public.csc_color_matrix.matrix);
ret = true;
}
}
return ret;
}
static void set_static_screen_events(struct dc *dc,
const struct dc_stream **stream,
int num_streams,
@ -373,6 +396,9 @@ static void allocate_dc_stream_funcs(struct core_dc *core_dc)
core_dc->public.stream_funcs.set_gamut_remap =
set_gamut_remap;
core_dc->public.stream_funcs.program_csc_matrix =
program_csc_matrix;
core_dc->public.stream_funcs.set_dither_option =
set_dither_option;

3
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -118,6 +118,9 @@ struct dc_stream_funcs {
bool (*set_gamut_remap)(struct dc *dc,
const struct dc_stream *stream);
bool (*program_csc_matrix)(struct dc *dc,
const struct dc_stream *stream);
void (*set_static_screen_events)(struct dc *dc,
const struct dc_stream **stream,
int num_streams,

23
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -1623,6 +1623,28 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
}
static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
enum dc_color_space colorspace,
uint16_t *matrix)
{
int i;
struct out_csc_color_matrix tbl_entry;
if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment
== true) {
enum dc_color_space color_space =
pipe_ctx->stream->public.output_color_space;
//uint16_t matrix[12];
for (i = 0; i < 12; i++)
tbl_entry.regval[i] = pipe_ctx->stream->public.csc_color_matrix.matrix[i];
tbl_entry.color_space = color_space;
//tbl_entry.regval = matrix;
pipe_ctx->opp->funcs->opp_set_csc_adjustment(pipe_ctx->opp, &tbl_entry);
}
}
static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
{
if (pipe_ctx->surface->public.visible)
@ -2103,6 +2125,7 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx,
static const struct hw_sequencer_funcs dcn10_funcs = {
.program_gamut_remap = program_gamut_remap,
.program_csc_matrix = program_csc_matrix,
.init_hw = init_hw,
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,

117
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
View File

@ -713,6 +713,48 @@ static void opp_power_on_regamma_lut(
}
void opp_set_output_csc_adjustment(
struct output_pixel_processor *opp,
const struct out_csc_color_matrix *tbl_entry)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
//enum csc_color_mode config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
uint32_t ocsc_mode = 4;
/**
*if (tbl_entry != NULL) {
* switch (tbl_entry->color_space) {
* case COLOR_SPACE_SRGB:
* case COLOR_SPACE_2020_RGB_FULLRANGE:
* ocsc_mode = 0;
* break;
* case COLOR_SPACE_SRGB_LIMITED:
* case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
* ocsc_mode = 1;
* break;
* case COLOR_SPACE_YCBCR601:
* case COLOR_SPACE_YCBCR601_LIMITED:
* ocsc_mode = 2;
* break;
* case COLOR_SPACE_YCBCR709:
* case COLOR_SPACE_YCBCR709_LIMITED:
* case COLOR_SPACE_2020_YCBCR:
* ocsc_mode = 3;
* break;
* case COLOR_SPACE_UNKNOWN:
* default:
* break;
* }
*}
*/
REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
program_color_matrix(oppn10, tbl_entry);
}
static void opp_program_regamma_lut(
struct output_pixel_processor *opp,
const struct pwl_result_data *rgb,
@ -736,6 +778,8 @@ static void opp_program_regamma_lut(
}
static bool opp_set_regamma_pwl(
struct output_pixel_processor *opp, const struct pwl_params *params)
{
@ -776,7 +820,7 @@ static void dcn10_opp_destroy(struct output_pixel_processor **opp)
static struct opp_funcs dcn10_opp_funcs = {
.opp_power_on_regamma_lut = opp_power_on_regamma_lut,
.opp_set_csc_adjustment = NULL,
.opp_set_csc_adjustment = opp_set_output_csc_adjustment,
.opp_set_csc_default = opp_set_output_csc_default,
.opp_set_dyn_expansion = opp_set_dyn_expansion,
.opp_program_regamma_pwl = opp_set_regamma_pwl,
@ -802,3 +846,74 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10,
oppn10->opp_shift = opp_shift;
oppn10->opp_mask = opp_mask;
}
void program_color_matrix(struct dcn10_opp *oppn10,
const struct out_csc_color_matrix *tbl_entry)
{
uint32_t mode;
REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
if (tbl_entry == NULL) {
BREAK_TO_DEBUGGER();
return;
}
if (mode == 4) {
/*R*/
REG_SET_2(CM_OCSC_C11_C12, 0,
CM_OCSC_C11, tbl_entry->regval[0],
CM_OCSC_C12, tbl_entry->regval[1]);
REG_SET_2(CM_OCSC_C13_C14, 0,
CM_OCSC_C13, tbl_entry->regval[2],
CM_OCSC_C14, tbl_entry->regval[3]);
/*G*/
REG_SET_2(CM_OCSC_C21_C22, 0,
CM_OCSC_C21, tbl_entry->regval[4],
CM_OCSC_C22, tbl_entry->regval[5]);
REG_SET_2(CM_OCSC_C23_C24, 0,
CM_OCSC_C23, tbl_entry->regval[6],
CM_OCSC_C24, tbl_entry->regval[7]);
/*B*/
REG_SET_2(CM_OCSC_C31_C32, 0,
CM_OCSC_C31, tbl_entry->regval[8],
CM_OCSC_C32, tbl_entry->regval[9]);
REG_SET_2(CM_OCSC_C33_C34, 0,
CM_OCSC_C33, tbl_entry->regval[10],
CM_OCSC_C34, tbl_entry->regval[11]);
} else {
/*R*/
REG_SET_2(CM_COMB_C11_C12, 0,
CM_COMB_C11, tbl_entry->regval[0],
CM_COMB_C12, tbl_entry->regval[1]);
REG_SET_2(CM_COMB_C13_C14, 0,
CM_COMB_C13, tbl_entry->regval[2],
CM_COMB_C14, tbl_entry->regval[3]);
/*G*/
REG_SET_2(CM_COMB_C21_C22, 0,
CM_COMB_C21, tbl_entry->regval[4],
CM_COMB_C22, tbl_entry->regval[5]);
REG_SET_2(CM_COMB_C23_C24, 0,
CM_COMB_C23, tbl_entry->regval[6],
CM_COMB_C24, tbl_entry->regval[7]);
/*B*/
REG_SET_2(CM_COMB_C31_C32, 0,
CM_COMB_C31, tbl_entry->regval[8],
CM_COMB_C32, tbl_entry->regval[9]);
REG_SET_2(CM_COMB_C33_C34, 0,
CM_COMB_C33, tbl_entry->regval[10],
CM_COMB_C34, tbl_entry->regval[11]);
}
}

76
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
View File

@ -34,6 +34,18 @@
.field_name = reg_name ## __ ## field_name ## post_fix
#define OPP_DCN10_REG_LIST(id) \
SRI(CM_OCSC_C11_C12, CM, id), \
SRI(CM_OCSC_C13_C14, CM, id), \
SRI(CM_OCSC_C21_C22, CM, id), \
SRI(CM_OCSC_C23_C24, CM, id), \
SRI(CM_OCSC_C31_C32, CM, id), \
SRI(CM_OCSC_C33_C34, CM, id), \
SRI(CM_COMB_C11_C12, CM, id), \
SRI(CM_COMB_C13_C14, CM, id), \
SRI(CM_COMB_C21_C22, CM, id), \
SRI(CM_COMB_C23_C24, CM, id), \
SRI(CM_COMB_C31_C32, CM, id), \
SRI(CM_COMB_C33_C34, CM, id), \
SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id), \
SRI(CM_RGAM_CONTROL, CM, id), \
SRI(OBUF_CONTROL, DSCL, id), \
@ -109,6 +121,30 @@
SRI(CM_RGAM_LUT_DATA, CM, id)
#define OPP_DCN10_MASK_SH_LIST(mask_sh) \
OPP_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \
OPP_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
OPP_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C13, mask_sh), \
OPP_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C14, mask_sh), \
OPP_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C21, mask_sh), \
OPP_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C22, mask_sh), \
OPP_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C23, mask_sh), \
OPP_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C24, mask_sh), \
OPP_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C31, mask_sh), \
OPP_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C32, mask_sh), \
OPP_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
OPP_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \
OPP_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh), \
OPP_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh), \
OPP_SF(CM0_CM_COMB_C13_C14, CM_COMB_C13, mask_sh), \
OPP_SF(CM0_CM_COMB_C13_C14, CM_COMB_C14, mask_sh), \
OPP_SF(CM0_CM_COMB_C21_C22, CM_COMB_C21, mask_sh), \
OPP_SF(CM0_CM_COMB_C21_C22, CM_COMB_C22, mask_sh), \
OPP_SF(CM0_CM_COMB_C23_C24, CM_COMB_C23, mask_sh), \
OPP_SF(CM0_CM_COMB_C23_C24, CM_COMB_C24, mask_sh), \
OPP_SF(CM0_CM_COMB_C31_C32, CM_COMB_C31, mask_sh), \
OPP_SF(CM0_CM_COMB_C31_C32, CM_COMB_C32, mask_sh), \
OPP_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh), \
OPP_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh), \
OPP_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
OPP_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \
OPP_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \
@ -314,6 +350,30 @@
OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
#define OPP_DCN10_REG_FIELD_LIST(type) \
type CM_OCSC_C11; \
type CM_OCSC_C12; \
type CM_OCSC_C13; \
type CM_OCSC_C14; \
type CM_OCSC_C21; \
type CM_OCSC_C22; \
type CM_OCSC_C23; \
type CM_OCSC_C24; \
type CM_OCSC_C31; \
type CM_OCSC_C32; \
type CM_OCSC_C33; \
type CM_OCSC_C34; \
type CM_COMB_C11; \
type CM_COMB_C12; \
type CM_COMB_C13; \
type CM_COMB_C14; \
type CM_COMB_C21; \
type CM_COMB_C22; \
type CM_COMB_C23; \
type CM_COMB_C24; \
type CM_COMB_C31; \
type CM_COMB_C32; \
type CM_COMB_C33; \
type CM_COMB_C34; \
type CM_RGAM_LUT_MODE; \
type OBUF_BYPASS; \
type OBUF_H_2X_UPSCALE_EN; \
@ -527,6 +587,18 @@ struct dcn10_opp_mask {
};
struct dcn10_opp_registers {
uint32_t CM_OCSC_C11_C12;
uint32_t CM_OCSC_C13_C14;
uint32_t CM_OCSC_C21_C22;
uint32_t CM_OCSC_C23_C24;
uint32_t CM_OCSC_C31_C32;
uint32_t CM_OCSC_C33_C34;
uint32_t CM_COMB_C11_C12;
uint32_t CM_COMB_C13_C14;
uint32_t CM_COMB_C21_C22;
uint32_t CM_COMB_C23_C24;
uint32_t CM_COMB_C31_C32;
uint32_t CM_COMB_C33_C34;
uint32_t CM_RGAM_LUT_WRITE_EN_MASK;
uint32_t CM_RGAM_CONTROL;
uint32_t OBUF_CONTROL;
@ -619,4 +691,8 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10,
const struct dcn10_opp_shift *opp_shift,
const struct dcn10_opp_mask *opp_mask);
void program_color_matrix(
struct dcn10_opp *oppn10,
const struct out_csc_color_matrix *tbl_entry);
#endif

5
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
View File

@ -1027,9 +1027,8 @@ static struct transform_funcs dcn10_transform_funcs = {
.transform_reset = transform_reset,
.transform_set_scaler = transform_set_scaler_manual_scale,
.transform_get_optimal_number_of_taps =
transform_get_optimal_number_of_taps,
.transform_set_gamut_remap = dcn_transform_set_gamut_remap
.transform_get_optimal_number_of_taps = transform_get_optimal_number_of_taps,
.transform_set_gamut_remap = dcn_transform_set_gamut_remap,
};
/*****************************************/

1
drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
View File

@ -180,6 +180,7 @@ struct transform_funcs {
struct transform *xfm,
const struct xfm_grph_csc_adjustment *adjust);
void (*transform_set_pixel_storage_depth)(
struct transform *xfm,
enum lb_pixel_depth depth,

5
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
View File

@ -70,6 +70,11 @@ struct hw_sequencer_funcs {
void (*program_gamut_remap)(
struct pipe_ctx *pipe_ctx);
void (*program_csc_matrix)(
struct pipe_ctx *pipe_ctx,
enum dc_color_space colorspace,
uint16_t *matrix);
void (*update_plane_addr)(
const struct core_dc *dc,
struct pipe_ctx *pipe_ctx);