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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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mailbox: bcm-pdc: Convert from interrupts to poll for tx done
The PDC driver is a mailbox controller. A mailbox controller can report that a mailbox message has been "transmitted" either when a tx interrupt fires or by having the mailbox framework poll. This commit converts the PDC driver to the poll method. We found that the tx interrupt happens when the descriptors are read by the SPU hw. Thus, the interrupt method does not allow more than one tx message in the PDC tx DMA ring at a time. To keep the SPU hw busy, we would like to keep the tx ring full under heavy load. With the poll method, the PDC driver responds that the previous message has been transmitted if the tx ring has space for another message. SPU request messages take a variable number of descriptors. If 15 descriptors are available, there is a good chance another message will fit. Also increased the ring size from 128 to 512 descriptors. With this change, I found the PDC driver hangs on its spinlock under heavy load. The PDC spinlock is not required; so I removed it. Calls to pdc_send_data() are already synchronized because of the channel spinlock in the mailbox framework. Other references to ring indexes should not require locking because they only written on either the tx or rx side. Signed-off-by: Rob Rice <rob.rice@broadcom.com> Reviewed-by: Andy Gospodarek <gospo@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Rob Rice
Jassi Brar
parent
9310f1ded4
commit
ab8d1b2d56
@ -60,7 +60,13 @@
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#define RING_ENTRY_SIZE sizeof(struct dma64dd)
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/* # entries in PDC dma ring */
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#define PDC_RING_ENTRIES 128
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#define PDC_RING_ENTRIES 512
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/*
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* Minimum number of ring descriptor entries that must be free to tell mailbox
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* framework that it can submit another request
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*/
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#define PDC_RING_SPACE_MIN 15
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#define PDC_RING_SIZE (PDC_RING_ENTRIES * RING_ENTRY_SIZE)
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/* Rings are 8k aligned */
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#define RING_ALIGN_ORDER 13
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@ -93,11 +99,9 @@
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* Interrupt mask and status definitions. Enable interrupts for tx and rx on
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* ring 0
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*/
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#define PDC_XMTINT_0 (24 + PDC_RINGSET)
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#define PDC_RCVINT_0 (16 + PDC_RINGSET)
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#define PDC_XMTINTEN_0 BIT(PDC_XMTINT_0)
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#define PDC_RCVINTEN_0 BIT(PDC_RCVINT_0)
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#define PDC_INTMASK (PDC_XMTINTEN_0 | PDC_RCVINTEN_0)
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#define PDC_INTMASK (PDC_RCVINTEN_0)
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#define PDC_LAZY_FRAMECOUNT 1
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#define PDC_LAZY_TIMEOUT 10000
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#define PDC_LAZY_INT (PDC_LAZY_TIMEOUT | (PDC_LAZY_FRAMECOUNT << 24))
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@ -258,9 +262,6 @@ struct pdc_ring_alloc {
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/* PDC state structure */
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struct pdc_state {
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/* synchronize access to this PDC state structure */
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spinlock_t pdc_lock;
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/* Index of the PDC whose state is in this structure instance */
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u8 pdc_idx;
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@ -401,11 +402,14 @@ struct pdc_state {
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struct dentry *debugfs_stats; /* debug FS stats file for this PDC */
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/* counters */
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u32 pdc_requests; /* number of request messages submitted */
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u32 pdc_replies; /* number of reply messages received */
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u32 txnobuf; /* count of tx ring full */
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u32 rxnobuf; /* count of rx ring full */
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u32 rx_oflow; /* count of rx overflows */
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u32 pdc_requests; /* number of request messages submitted */
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u32 pdc_replies; /* number of reply messages received */
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u32 last_tx_not_done; /* too few tx descriptors to indicate done */
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u32 tx_ring_full; /* unable to accept msg because tx ring full */
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u32 rx_ring_full; /* unable to accept msg because rx ring full */
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u32 txnobuf; /* unable to create tx descriptor */
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u32 rxnobuf; /* unable to create rx descriptor */
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u32 rx_oflow; /* count of rx overflows */
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};
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/* Global variables */
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@ -438,20 +442,33 @@ static ssize_t pdc_debugfs_read(struct file *filp, char __user *ubuf,
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out_offset += snprintf(buf + out_offset, out_count - out_offset,
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"SPU %u stats:\n", pdcs->pdc_idx);
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out_offset += snprintf(buf + out_offset, out_count - out_offset,
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"PDC requests............%u\n",
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"PDC requests....................%u\n",
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pdcs->pdc_requests);
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out_offset += snprintf(buf + out_offset, out_count - out_offset,
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"PDC responses...........%u\n",
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"PDC responses...................%u\n",
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pdcs->pdc_replies);
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out_offset += snprintf(buf + out_offset, out_count - out_offset,
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"Tx err ring full........%u\n",
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"Tx not done.....................%u\n",
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pdcs->last_tx_not_done);
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out_offset += snprintf(buf + out_offset, out_count - out_offset,
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"Tx ring full....................%u\n",
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pdcs->tx_ring_full);
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out_offset += snprintf(buf + out_offset, out_count - out_offset,
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"Rx ring full....................%u\n",
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pdcs->rx_ring_full);
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out_offset += snprintf(buf + out_offset, out_count - out_offset,
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"Tx desc write fail. Ring full...%u\n",
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pdcs->txnobuf);
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out_offset += snprintf(buf + out_offset, out_count - out_offset,
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"Rx err ring full........%u\n",
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"Rx desc write fail. Ring full...%u\n",
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pdcs->rxnobuf);
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out_offset += snprintf(buf + out_offset, out_count - out_offset,
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"Receive overflow........%u\n",
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"Receive overflow................%u\n",
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pdcs->rx_oflow);
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out_offset += snprintf(buf + out_offset, out_count - out_offset,
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"Num frags in rx ring............%u\n",
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NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr,
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pdcs->nrxpost));
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if (out_offset > out_count)
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out_offset = out_count;
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@ -582,8 +599,6 @@ pdc_receive(struct pdc_state *pdcs, struct brcm_message *mssg)
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u32 rx_idx; /* ring index of start of receive frame */
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dma_addr_t resp_hdr_daddr;
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spin_lock(&pdcs->pdc_lock);
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/*
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* return if a complete response message is not yet ready.
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* rxin_numd[rxin] is the number of fragments in the next msg
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@ -600,7 +615,6 @@ pdc_receive(struct pdc_state *pdcs, struct brcm_message *mssg)
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if ((frags_rdy == 0) ||
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(frags_rdy < pdcs->rxin_numd[pdcs->rxin])) {
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/* No response ready */
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spin_unlock(&pdcs->pdc_lock);
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return -EAGAIN;
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}
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/* can't read descriptors/data until write index is read */
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@ -630,8 +644,6 @@ pdc_receive(struct pdc_state *pdcs, struct brcm_message *mssg)
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for (i = 0; i < num_frags; i++)
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pdcs->rxin = NEXTRXD(pdcs->rxin, pdcs->nrxpost);
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spin_unlock(&pdcs->pdc_lock);
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dev_dbg(dev, "PDC %u reclaimed %d rx descriptors",
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pdcs->pdc_idx, num_frags);
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@ -920,8 +932,6 @@ static irqreturn_t pdc_irq_handler(int irq, void *cookie)
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struct pdc_state *pdcs = cookie;
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u32 intstatus = ioread32(pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET);
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if (intstatus & PDC_XMTINTEN_0)
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set_bit(PDC_XMTINT_0, &pdcs->intstatus);
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if (intstatus & PDC_RCVINTEN_0)
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set_bit(PDC_RCVINT_0, &pdcs->intstatus);
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@ -953,45 +963,35 @@ static irqreturn_t pdc_irq_thread(int irq, void *cookie)
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struct pdc_state *pdcs = cookie;
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struct mbox_controller *mbc;
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struct mbox_chan *chan;
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bool tx_int;
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bool rx_int;
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int rx_status;
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struct brcm_message mssg;
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tx_int = test_and_clear_bit(PDC_XMTINT_0, &pdcs->intstatus);
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rx_int = test_and_clear_bit(PDC_RCVINT_0, &pdcs->intstatus);
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if (pdcs && (tx_int || rx_int)) {
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if (pdcs && rx_int) {
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dev_dbg(&pdcs->pdev->dev,
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"%s() got irq %d with tx_int %s, rx_int %s",
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__func__, irq,
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tx_int ? "set" : "clear", rx_int ? "set" : "clear");
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"%s() got irq %d with rx_int %s",
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__func__, irq, rx_int ? "set" : "clear");
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mbc = &pdcs->mbc;
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chan = &mbc->chans[0];
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if (tx_int) {
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dev_dbg(&pdcs->pdev->dev, "%s(): tx done", __func__);
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/* only one frame in flight at a time */
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mbox_chan_txdone(chan, PDC_SUCCESS);
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}
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if (rx_int) {
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while (1) {
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/* Could be many frames ready */
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memset(&mssg, 0, sizeof(mssg));
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mssg.type = BRCM_MESSAGE_SPU;
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rx_status = pdc_receive(pdcs, &mssg);
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if (rx_status >= 0) {
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dev_dbg(&pdcs->pdev->dev,
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"%s(): invoking client rx cb",
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__func__);
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mbox_chan_received_data(chan, &mssg);
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} else {
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dev_dbg(&pdcs->pdev->dev,
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"%s(): no SPU response available",
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__func__);
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break;
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}
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while (1) {
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/* Could be many frames ready */
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memset(&mssg, 0, sizeof(mssg));
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mssg.type = BRCM_MESSAGE_SPU;
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rx_status = pdc_receive(pdcs, &mssg);
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if (rx_status >= 0) {
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dev_dbg(&pdcs->pdev->dev,
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"%s(): invoking client rx cb",
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__func__);
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mbox_chan_received_data(chan, &mssg);
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} else {
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dev_dbg(&pdcs->pdev->dev,
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"%s(): no SPU response available",
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__func__);
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break;
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}
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}
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return IRQ_HANDLED;
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@ -1036,9 +1036,6 @@ static int pdc_ring_init(struct pdc_state *pdcs, int ringset)
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dev_dbg(dev, " - base DMA addr of rx ring %pad", &rx.dmabase);
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dev_dbg(dev, " - base virtual addr of rx ring %p", rx.vbase);
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/* lock after ring allocation to avoid scheduling while atomic */
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spin_lock(&pdcs->pdc_lock);
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memcpy(&pdcs->tx_ring_alloc, &tx, sizeof(tx));
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memcpy(&pdcs->rx_ring_alloc, &rx, sizeof(rx));
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@ -1103,7 +1100,6 @@ static int pdc_ring_init(struct pdc_state *pdcs, int ringset)
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(void *)&pdcs->rxd_64[i].ctrl1);
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}
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}
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spin_unlock(&pdcs->pdc_lock);
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return PDC_SUCCESS;
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fail_dealloc:
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@ -1127,6 +1123,80 @@ static void pdc_ring_free(struct pdc_state *pdcs)
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}
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}
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/**
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* pdc_desc_count() - Count the number of DMA descriptors that will be required
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* for a given scatterlist. Account for the max length of a DMA buffer.
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* @sg: Scatterlist to be DMA'd
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* Return: Number of descriptors required
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*/
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static u32 pdc_desc_count(struct scatterlist *sg)
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{
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u32 cnt = 0;
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while (sg) {
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cnt += ((sg->length / PDC_DMA_BUF_MAX) + 1);
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sg = sg_next(sg);
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}
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return cnt;
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}
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/**
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* pdc_rings_full() - Check whether the tx ring has room for tx_cnt descriptors
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* and the rx ring has room for rx_cnt descriptors.
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* @pdcs: PDC state
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* @tx_cnt: The number of descriptors required in the tx ring
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* @rx_cnt: The number of descriptors required i the rx ring
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*
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* Return: true if one of the rings does not have enough space
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* false if sufficient space is available in both rings
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*/
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static bool pdc_rings_full(struct pdc_state *pdcs, int tx_cnt, int rx_cnt)
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{
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u32 rx_avail;
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u32 tx_avail;
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bool full = false;
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/* Check if the tx and rx rings are likely to have enough space */
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rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout,
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pdcs->nrxpost);
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if (unlikely(rx_cnt > rx_avail)) {
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pdcs->rx_ring_full++;
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full = true;
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}
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if (likely(!full)) {
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tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout,
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pdcs->ntxpost);
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if (unlikely(tx_cnt > tx_avail)) {
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pdcs->tx_ring_full++;
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full = true;
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}
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}
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return full;
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}
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/**
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* pdc_last_tx_done() - If both the tx and rx rings have at least
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* PDC_RING_SPACE_MIN descriptors available, then indicate that the mailbox
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* framework can submit another message.
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* @chan: mailbox channel to check
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* Return: true if PDC can accept another message on this channel
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*/
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static bool pdc_last_tx_done(struct mbox_chan *chan)
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{
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struct pdc_state *pdcs = chan->con_priv;
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bool ret;
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if (unlikely(pdc_rings_full(pdcs, PDC_RING_SPACE_MIN,
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PDC_RING_SPACE_MIN))) {
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pdcs->last_tx_not_done++;
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ret = false;
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} else {
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ret = true;
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}
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return ret;
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}
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/**
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* pdc_send_data() - mailbox send_data function
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* @chan: The mailbox channel on which the data is sent. The channel
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@ -1158,6 +1228,8 @@ static int pdc_send_data(struct mbox_chan *chan, void *data)
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int src_nent;
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int dst_nent;
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int nent;
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u32 tx_desc_req;
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u32 rx_desc_req;
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if (mssg->type != BRCM_MESSAGE_SPU)
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return -ENOTSUPP;
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@ -1180,7 +1252,19 @@ static int pdc_send_data(struct mbox_chan *chan, void *data)
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}
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}
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spin_lock(&pdcs->pdc_lock);
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/*
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* Check if the tx and rx rings have enough space. Do this prior to
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* writing any tx or rx descriptors. Need to ensure that we do not write
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* a partial set of descriptors, or write just rx descriptors but
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* corresponding tx descriptors don't fit. Note that we want this check
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* and the entire sequence of descriptor to happen without another
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* thread getting in. The channel spin lock in the mailbox framework
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* ensures this.
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*/
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tx_desc_req = pdc_desc_count(mssg->spu.src);
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rx_desc_req = pdc_desc_count(mssg->spu.dst);
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if (pdc_rings_full(pdcs, tx_desc_req, rx_desc_req + 1))
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return -ENOSPC;
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/* Create rx descriptors to SPU catch response */
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err = pdc_rx_list_init(pdcs, mssg->spu.dst, mssg->ctx);
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@ -1190,8 +1274,6 @@ static int pdc_send_data(struct mbox_chan *chan, void *data)
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err |= pdc_tx_list_sg_add(pdcs, mssg->spu.src);
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err |= pdc_tx_list_final(pdcs); /* initiate transfer */
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spin_unlock(&pdcs->pdc_lock);
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if (err)
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dev_err(&pdcs->pdev->dev,
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"%s failed with error %d", __func__, err);
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@ -1359,6 +1441,7 @@ static int pdc_interrupts_init(struct pdc_state *pdcs)
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static const struct mbox_chan_ops pdc_mbox_chan_ops = {
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.send_data = pdc_send_data,
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.last_tx_done = pdc_last_tx_done,
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.startup = pdc_startup,
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.shutdown = pdc_shutdown
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};
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@ -1391,8 +1474,9 @@ static int pdc_mb_init(struct pdc_state *pdcs)
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if (!mbc->chans)
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return -ENOMEM;
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mbc->txdone_irq = true;
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mbc->txdone_poll = false;
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mbc->txdone_irq = false;
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mbc->txdone_poll = true;
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mbc->txpoll_period = 1;
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for (chan_index = 0; chan_index < mbc->num_chans; chan_index++)
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mbc->chans[chan_index].con_priv = pdcs;
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@ -1462,7 +1546,6 @@ static int pdc_probe(struct platform_device *pdev)
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goto cleanup;
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}
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spin_lock_init(&pdcs->pdc_lock);
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pdcs->pdev = pdev;
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platform_set_drvdata(pdev, pdcs);
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pdcs->pdc_idx = pdcg.num_spu;
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