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MIPS: bitops: Avoid redundant zero-comparison for non-LLSC
The IRQ-disabling non-LLSC fallbacks for bitops on UP systems already return a zero or one, so there's no need to perform another comparison against zero. Move these comparisons into the LLSC paths to avoid the redundant work. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: linux-kernel@vger.kernel.org
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@ -264,6 +264,8 @@ static inline int test_and_set_bit_lock(unsigned long nr,
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: "=&r" (temp), "+m" (*m), "=&r" (res)
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: "ir" (BIT(bit))
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: __LLSC_CLOBBER);
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res = res != 0;
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} else {
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loongson_llsc_mb();
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do {
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@ -279,12 +281,12 @@ static inline int test_and_set_bit_lock(unsigned long nr,
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: __LLSC_CLOBBER);
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} while (unlikely(!res));
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res = temp & BIT(bit);
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res = (temp & BIT(bit)) != 0;
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}
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smp_llsc_mb();
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return res != 0;
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return res;
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}
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/*
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@ -335,6 +337,8 @@ static inline int test_and_clear_bit(unsigned long nr,
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
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: "ir" (BIT(bit))
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: __LLSC_CLOBBER);
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res = res != 0;
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} else if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(nr)) {
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loongson_llsc_mb();
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do {
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@ -363,12 +367,12 @@ static inline int test_and_clear_bit(unsigned long nr,
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: __LLSC_CLOBBER);
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} while (unlikely(!res));
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res = temp & BIT(bit);
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res = (temp & BIT(bit)) != 0;
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}
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smp_llsc_mb();
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return res != 0;
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return res;
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}
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/*
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@ -403,6 +407,8 @@ static inline int test_and_change_bit(unsigned long nr,
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
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: "ir" (BIT(bit))
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: __LLSC_CLOBBER);
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res = res != 0;
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} else {
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loongson_llsc_mb();
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do {
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@ -418,12 +424,12 @@ static inline int test_and_change_bit(unsigned long nr,
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: __LLSC_CLOBBER);
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} while (unlikely(!res));
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res = temp & BIT(bit);
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res = (temp & BIT(bit)) != 0;
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}
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smp_llsc_mb();
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return res != 0;
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return res;
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}
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#include <asm-generic/bitops/non-atomic.h>
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