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ARM: dts: r8a7745: Add APMU node and second CPU core

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Add DT node for the Advanced Power Management Unit (APMU), add the
second CPU core, and use "renesas,apmu" as "enable-method".

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Fabrizio Castro 2017-12-06 12:05:29 +00:00 committed by Simon Horman
parent 7f32eddb81
commit aaca1ff0db
1 changed files with 16 additions and 0 deletions
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16
arch/arm/boot/dts/r8a7745.dtsi
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@ -38,6 +38,7 @@ aliases {
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@ -49,6 +50,15 @@ cpu0: cpu@0 {
next-level-cache = <&L2_CA7>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <1>;
clock-frequency = <1000000000>;
power-domains = <&sysc R8A7745_PD_CA7_CPU1>;
next-level-cache = <&L2_CA7>;
};
L2_CA7: cache-controller-0 {
compatible = "cache";
cache-unified;
@ -65,6 +75,12 @@ soc {
#size-cells = <2>;
ranges;
apmu@e6151000 {
compatible = "renesas,r8a7745-apmu", "renesas,apmu";
reg = <0 0xe6151000 0 0x188>;
cpus = <&cpu0 &cpu1>;
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;