mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 16:46:41 +07:00
Merge branch 'x86/cpu' into x86/x2apic
Conflicts: arch/x86/kernel/cpu/feature_names.c include/asm-x86/cpufeature.h
This commit is contained in:
H. Peter Anvin
commit
aa3341a168
@ -15,7 +15,7 @@
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#include <stdio.h>
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#include "../kernel/cpu/feature_names.c"
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#include "../kernel/cpu/capflags.c"
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#if NCAPFLAGS > 8
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# error "Need to adjust the boot code handling of CPUID strings"
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@ -3,7 +3,7 @@
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#
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obj-y := intel_cacheinfo.o addon_cpuid_features.o
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obj-y += proc.o feature_names.o
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obj-y += proc.o capflags.o powerflags.o
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obj-$(CONFIG_X86_32) += common.o bugs.o cmpxchg.o
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obj-$(CONFIG_X86_64) += common_64.o bugs_64.o
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@ -23,3 +23,12 @@ obj-$(CONFIG_MTRR) += mtrr/
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obj-$(CONFIG_CPU_FREQ) += cpufreq/
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obj-$(CONFIG_X86_LOCAL_APIC) += perfctr-watchdog.o
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quiet_cmd_mkcapflags = MKCAP $@
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cmd_mkcapflags = $(PERL) $(srctree)/$(src)/mkcapflags.pl $< $@
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cpufeature = $(src)/../../../../include/asm-x86/cpufeature.h
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targets += capflags.c
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$(obj)/capflags.c: $(cpufeature) $(src)/mkcapflags.pl FORCE
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$(call if_changed,mkcapflags)
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@ -1,84 +0,0 @@
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/*
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* Strings for the various x86 capability flags.
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*
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* This file must not contain any executable code.
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*/
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#include <asm/cpufeature.h>
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/*
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* These flag bits must match the definitions in <asm/cpufeature.h>.
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* NULL means this bit is undefined or reserved; either way it doesn't
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* have meaning as far as Linux is concerned. Note that it's important
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* to realize there is a difference between this table and CPUID -- if
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* applications want to get the raw CPUID data, they should access
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* /dev/cpu/<cpu_nr>/cpuid instead.
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*/
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const char * const x86_cap_flags[NCAPINTS*32] = {
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/* Intel-defined */
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"fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
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"cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
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"pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
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"fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
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/* AMD-defined */
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, "mp", "nx", NULL, "mmxext", NULL,
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NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
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"3dnowext", "3dnow",
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/* Transmeta-defined */
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"recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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/* Other (Linux-defined) */
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"cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
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NULL, NULL, NULL, NULL,
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"constant_tsc", "up", NULL, "arch_perfmon",
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"pebs", "bts", NULL, NULL,
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"rep_good", NULL, NULL, NULL,
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"nopl", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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/* Intel-defined (#2) */
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"pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
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"tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
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NULL, NULL, "dca", "sse4_1", "sse4_2", "x2apic", NULL, "popcnt",
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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/* VIA/Cyrix/Centaur-defined */
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NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
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"ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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/* AMD-defined (#2) */
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"lahf_lm", "cmp_legacy", "svm", "extapic",
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"cr8_legacy", "abm", "sse4a", "misalignsse",
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"3dnowprefetch", "osvw", "ibs", "sse5",
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"skinit", "wdt", NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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/* Auxiliary (Linux-defined) */
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"ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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};
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const char *const x86_power_flags[32] = {
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"ts", /* temperature sensor */
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"fid", /* frequency id control */
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"vid", /* voltage id control */
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"ttp", /* thermal trip */
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"tm",
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"stc",
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"100mhzsteps",
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"hwpstate",
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"", /* tsc invariant mapped to constant_tsc */
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/* nothing */
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};
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32
arch/x86/kernel/cpu/mkcapflags.pl
Normal file
32
arch/x86/kernel/cpu/mkcapflags.pl
Normal file
@ -0,0 +1,32 @@
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#!/usr/bin/perl
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#
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# Generate the x86_cap_flags[] array from include/asm-x86/cpufeature.h
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#
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($in, $out) = @ARGV;
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open(IN, "< $in\0") or die "$0: cannot open: $in: $!\n";
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open(OUT, "> $out\0") or die "$0: cannot create: $out: $!\n";
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print OUT "#include <asm/cpufeature.h>\n\n";
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print OUT "const char * const x86_cap_flags[NCAPINTS*32] = {\n";
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while (defined($line = <IN>)) {
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if ($line =~ /^\s*\#\s*define\s+(X86_FEATURE_(\S+))\s+(.*)$/) {
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$macro = $1;
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$feature = $2;
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$tail = $3;
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if ($tail =~ /\/\*\s*\"([^"]*)\".*\*\//) {
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$feature = $1;
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}
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if ($feature ne '') {
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printf OUT "\t%-32s = \"%s\",\n",
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"[$macro]", "\L$feature";
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}
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}
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}
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print OUT "};\n";
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close(IN);
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close(OUT);
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20
arch/x86/kernel/cpu/powerflags.c
Normal file
20
arch/x86/kernel/cpu/powerflags.c
Normal file
@ -0,0 +1,20 @@
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/*
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* Strings for the various x86 power flags
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*
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* This file must not contain any executable code.
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*/
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#include <asm/cpufeature.h>
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const char *const x86_power_flags[32] = {
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"ts", /* temperature sensor */
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"fid", /* frequency id control */
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"vid", /* voltage id control */
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"ttp", /* thermal trip */
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"tm",
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"stc",
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"100mhzsteps",
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"hwpstate",
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"", /* tsc invariant mapped to constant_tsc */
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/* nothing */
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};
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@ -8,13 +8,19 @@
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#define NCAPINTS 8 /* N 32-bit words worth of info */
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/*
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* Note: If the comment begins with a quoted string, that string is used
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* in /proc/cpuinfo instead of the macro name. If the string is "",
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* this feature bit is not displayed in /proc/cpuinfo at all.
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*/
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/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
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#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
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#define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
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#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
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#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
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#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
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#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
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#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers */
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#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
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#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */
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#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
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@ -23,22 +29,23 @@
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#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
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#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
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#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
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#define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
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#define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions */
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/* (plus FCMOVcc, FCOMI with FPU) */
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#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
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#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
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#define X86_FEATURE_PN (0*32+18) /* Processor serial number */
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#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */
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#define X86_FEATURE_DS (0*32+21) /* Debug Store */
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#define X86_FEATURE_CLFLSH (0*32+19) /* "clflush" CLFLUSH instruction */
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#define X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */
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#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
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#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
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#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
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/* of FPU context), and CR4.OSFXSR available */
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#define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */
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#define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */
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#define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */
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#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
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#define X86_FEATURE_XMM (0*32+25) /* "sse" */
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#define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */
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#define X86_FEATURE_SELFSNOOP (0*32+27) /* "ss" CPU self snoop */
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#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
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#define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */
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#define X86_FEATURE_ACC (0*32+29) /* "tm" Automatic clock control */
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#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
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#define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
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/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
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/* Don't duplicate feature flags which are redundant with Intel! */
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@ -46,7 +53,8 @@
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#define X86_FEATURE_MP (1*32+19) /* MP Capable. */
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#define X86_FEATURE_NX (1*32+20) /* Execute Disable */
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#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
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#define X86_FEATURE_GBPAGES (1*32+26) /* GB pages */
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#define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSAVE/FXRSTOR optimizations */
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#define X86_FEATURE_GBPAGES (1*32+26) /* "pdpe1gb" GB pages */
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#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
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#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
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#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
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@ -64,54 +72,77 @@
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#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
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#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
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/* cpu types for specific tunings: */
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#define X86_FEATURE_K8 (3*32+ 4) /* Opteron, Athlon64 */
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#define X86_FEATURE_K7 (3*32+ 5) /* Athlon */
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#define X86_FEATURE_P3 (3*32+ 6) /* P3 */
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#define X86_FEATURE_P4 (3*32+ 7) /* P4 */
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#define X86_FEATURE_K8 (3*32+ 4) /* "" Opteron, Athlon64 */
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#define X86_FEATURE_K7 (3*32+ 5) /* "" Athlon */
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#define X86_FEATURE_P3 (3*32+ 6) /* "" P3 */
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#define X86_FEATURE_P4 (3*32+ 7) /* "" P4 */
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#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
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#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */
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#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */
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#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
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#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
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#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
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#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
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#define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */
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#define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */
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#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
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#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
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#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
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#define X86_FEATURE_11AP (3*32+19) /* Bad local APIC aka 11AP */
|
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#define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */
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#define X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in ia32 userspace */
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#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */
|
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#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */
|
||||
#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
|
||||
#define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */
|
||||
#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
|
||||
#define X86_FEATURE_XTOPOLOGY (3*32+21) /* cpu topology enum extensions */
|
||||
|
||||
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
|
||||
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
|
||||
#define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */
|
||||
#define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */
|
||||
#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
|
||||
#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */
|
||||
#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
|
||||
#define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */
|
||||
#define X86_FEATURE_DSCPL (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
|
||||
#define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */
|
||||
#define X86_FEATURE_SMX (4*32+ 6) /* Safer mode */
|
||||
#define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */
|
||||
#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
|
||||
#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */
|
||||
#define X86_FEATURE_CID (4*32+10) /* Context ID */
|
||||
#define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */
|
||||
#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
|
||||
#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
|
||||
#define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */
|
||||
#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
|
||||
#define X86_FEATURE_XMM4_2 (4*32+20) /* Streaming SIMD Extensions-4.2 */
|
||||
#define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */
|
||||
#define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */
|
||||
#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */
|
||||
#define X86_FEATURE_AES (4*32+25) /* AES instructions */
|
||||
#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
|
||||
#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */
|
||||
#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
|
||||
|
||||
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
|
||||
#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
|
||||
#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */
|
||||
#define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
|
||||
#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */
|
||||
#define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */
|
||||
#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* "rng_en" RNG enabled */
|
||||
#define X86_FEATURE_XCRYPT (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
|
||||
#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* "ace_en" on-CPU crypto enabled */
|
||||
#define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */
|
||||
#define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */
|
||||
#define X86_FEATURE_PHE (5*32+ 10) /* PadLock Hash Engine */
|
||||
#define X86_FEATURE_PHE_EN (5*32+ 11) /* PHE enabled */
|
||||
#define X86_FEATURE_PMM (5*32+ 12) /* PadLock Montgomery Multiplier */
|
||||
#define X86_FEATURE_PMM_EN (5*32+ 13) /* PMM enabled */
|
||||
#define X86_FEATURE_PHE (5*32+10) /* PadLock Hash Engine */
|
||||
#define X86_FEATURE_PHE_EN (5*32+11) /* PHE enabled */
|
||||
#define X86_FEATURE_PMM (5*32+12) /* PadLock Montgomery Multiplier */
|
||||
#define X86_FEATURE_PMM_EN (5*32+13) /* PMM enabled */
|
||||
|
||||
/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
|
||||
#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
|
||||
#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
|
||||
#define X86_FEATURE_IBS (6*32+ 10) /* Instruction Based Sampling */
|
||||
#define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */
|
||||
#define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */
|
||||
#define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */
|
||||
#define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */
|
||||
#define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */
|
||||
#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
|
||||
#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
|
||||
#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */
|
||||
#define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */
|
||||
#define X86_FEATURE_SSE5 (6*32+11) /* SSE-5 */
|
||||
#define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */
|
||||
#define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */
|
||||
|
||||
/*
|
||||
* Auxiliary flags: Linux defined - For features scattered in various
|
||||
@ -152,7 +183,7 @@ extern const char * const x86_power_flags[32];
|
||||
} while (0)
|
||||
#define setup_force_cpu_cap(bit) do { \
|
||||
set_cpu_cap(&boot_cpu_data, bit); \
|
||||
clear_bit(bit, (unsigned long *)cleared_cpu_caps); \
|
||||
clear_bit(bit, (unsigned long *)cleared_cpu_caps); \
|
||||
} while (0)
|
||||
|
||||
#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)
|
||||
@ -193,8 +224,10 @@ extern const char * const x86_power_flags[32];
|
||||
#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
|
||||
#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
|
||||
#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
|
||||
#define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1)
|
||||
#define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2)
|
||||
#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
|
||||
#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
|
||||
|
||||
#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
|
||||
# define cpu_has_invlpg 1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user