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ath9k_hw: Fix a reset failure on AR9382 (2x2).

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AR9382 needs to be configured for the correct chain mask before
running AGC/TxIQ caliberation. Otherwise reset would fail.

Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com>
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Senthil Balasubramanian 2010-11-11 00:40:33 -08:00 committed by John W. Linville
parent 72a801103f
commit a9d85fbd3e
2 changed files with 14 additions and 5 deletions
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17
drivers/net/wireless/ath/ath9k/ar9003_calib.c
View File

@ -718,12 +718,19 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
struct ath9k_channel *chan)
{
struct ath_common *common = ath9k_hw_common(ah);
int val;
/*
* 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
* running AGC/TxIQ cals
*/
ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
val = REG_READ(ah, AR_ENT_OTP);
ath_print(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val);
if (val & AR_ENT_OTP_CHAIN2_DISABLE)
ar9003_hw_set_chain_masks(ah, 0x3, 0x3);
else
/*
* 0x7 = 0b111 , AR9003 needs to be configured for 3-chain
* mode before running AGC/TxIQ cals
*/
ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
/* Do Tx IQ Calibration */
ar9003_hw_tx_iq_cal(ah);

2
drivers/net/wireless/ath/ath9k/reg.h
View File

@ -1065,6 +1065,8 @@ enum {
#define AR_INTR_PRIO_ASYNC_MASK 0x40c8
#define AR_INTR_PRIO_SYNC_MASK 0x40cc
#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
#define AR_ENT_OTP 0x40d8
#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
#define AR_RTC_9300_PLL_DIV 0x000003ff
#define AR_RTC_9300_PLL_DIV_S 0