AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-11-27 00:20:58 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

ARM: mvebu: add Device Tree for the Armada 385 RD board

Browse Source 
The Armada 385 RD board is the reference design board from Marvell
for the Armada 385 SoC. This commit adds a Device Tree description for
this board, which enables the following features:

 * Network interfaces
 * I2C bus
 * Serial port
 * SPI bus, with a SPI flash
 * PCIe interface

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Gregory CLEMENT 2014-03-06 16:17:55 +01:00 committed by Jason Cooper
parent 0d2e63782c
commit a8a921dd22
2 changed files with 96 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boot/dts/Makefile
View File

@ -152,7 +152,8 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-db.dtb
armada-385-db.dtb \
armada-385-rd.dtb
dtb-$(CONFIG_MACH_ARMADA_XP) += \
armada-xp-axpwifiap.dtb \
armada-xp-db.dtb \

94
arch/arm/boot/dts/armada-385-rd.dts Normal file
View File

@ -0,0 +1,94 @@
/*
* Device Tree file for Marvell Armada 385 Reference Design board
* (RD-88F6820-AP)
*
* Copyright (C) 2014 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "armada-385.dtsi"
/ {
model = "Marvell Armada 385 Reference Design";
compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>; /* 256 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
spi@10600 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
i2c@11000 {
status = "okay";
clock-frequency = <100000>;
};
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
ethernet@30000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@70000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
pcie-controller {
status = "okay";
/*
* One PCIe units is accessible through
* standard PCIe slot on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
};
};