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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge branch 'timer-add-fsleep-for-flexible-sleeping'
Heiner Kallweit says: ==================== timer: add fsleep for flexible sleeping Sleeping for a certain amount of time requires use of different functions, depending on the time period. Documentation/timers/timers-howto.rst explains when to use which function, and also checkpatch checks for some potentially problematic cases. So let's create a helper that automatically chooses the appropriate sleep function -> fsleep(), for flexible sleeping Not sure why such a helper doesn't exist yet, or where the pitfall is, because it's a quite obvious idea. If the delay is a constant, then the compiler should be able to ensure that the new helper doesn't create overhead. If the delay is not constant, then the new helper can save some code. First user is the r8169 network driver. If nothing speaks against it, then this series could go through the netdev tree. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
a88845d862
@ -110,3 +110,6 @@ NON-ATOMIC CONTEXT:
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short, the difference is whether the sleep can be ended
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early by a signal. In general, just use msleep unless
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you know you have a need for the interruptible variant.
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FLEXIBLE SLEEPING (any delay, uninterruptible)
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* Use fsleep
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@ -724,55 +724,35 @@ struct rtl_cond {
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const char *msg;
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};
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static void rtl_udelay(unsigned int d)
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{
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udelay(d);
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}
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static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
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void (*delay)(unsigned int), unsigned int d, int n,
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bool high)
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unsigned long usecs, int n, bool high)
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{
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int i;
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for (i = 0; i < n; i++) {
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if (c->check(tp) == high)
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return true;
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delay(d);
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fsleep(usecs);
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}
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if (net_ratelimit())
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netdev_err(tp->dev, "%s == %d (loop: %d, delay: %d).\n",
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c->msg, !high, n, d);
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netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
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c->msg, !high, n, usecs);
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return false;
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}
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static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
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const struct rtl_cond *c,
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unsigned int d, int n)
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static bool rtl_loop_wait_high(struct rtl8169_private *tp,
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const struct rtl_cond *c,
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unsigned long d, int n)
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{
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return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
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return rtl_loop_wait(tp, c, d, n, true);
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}
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static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
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const struct rtl_cond *c,
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unsigned int d, int n)
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static bool rtl_loop_wait_low(struct rtl8169_private *tp,
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const struct rtl_cond *c,
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unsigned long d, int n)
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{
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return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
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}
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static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
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const struct rtl_cond *c,
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unsigned int d, int n)
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{
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return rtl_loop_wait(tp, c, msleep, d, n, true);
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}
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static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
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const struct rtl_cond *c,
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unsigned int d, int n)
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{
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return rtl_loop_wait(tp, c, msleep, d, n, false);
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return rtl_loop_wait(tp, c, d, n, false);
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}
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#define DECLARE_RTL_COND(name) \
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@ -807,7 +787,7 @@ static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
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RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
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rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
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rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
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}
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static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
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@ -817,7 +797,7 @@ static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
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RTL_W32(tp, GPHY_OCP, reg << 15);
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return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
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return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
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(RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
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}
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@ -895,7 +875,7 @@ static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
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{
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RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
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rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
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rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
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/*
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* According to hardware specs a 20us delay is required after write
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* complete indication, but before sending next command.
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@ -909,7 +889,7 @@ static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
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RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
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value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
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value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
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RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
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/*
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@ -932,7 +912,7 @@ static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
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RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
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RTL_W32(tp, EPHY_RXER_NUM, 0);
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rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
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rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
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}
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static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
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@ -949,7 +929,7 @@ static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
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RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
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RTL_W32(tp, EPHY_RXER_NUM, 0);
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return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
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return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
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RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
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}
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@ -1035,7 +1015,7 @@ static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
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RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
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(reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
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rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
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rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
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udelay(10);
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}
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@ -1044,7 +1024,7 @@ static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
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{
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RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
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return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
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return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
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RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
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}
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@ -1060,7 +1040,7 @@ static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
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RTL_W32(tp, ERIDR, val);
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RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
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rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
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rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
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}
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static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
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@ -1073,7 +1053,7 @@ static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
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{
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RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
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return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
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return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
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RTL_R32(tp, ERIDR) : ~0;
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}
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@ -1106,7 +1086,7 @@ static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
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static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
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{
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RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
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return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
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return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
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RTL_R32(tp, OCPDR) : ~0;
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}
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@ -1120,7 +1100,7 @@ static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
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{
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RTL_W32(tp, OCPDR, data);
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RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
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rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
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rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
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}
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static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
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@ -1168,7 +1148,7 @@ DECLARE_RTL_COND(rtl_ocp_tx_cond)
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static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
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{
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RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
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rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
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rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
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RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
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RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
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}
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@ -1176,7 +1156,7 @@ static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
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static void rtl8168dp_driver_start(struct rtl8169_private *tp)
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{
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r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
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rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
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rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
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}
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static void rtl8168ep_driver_start(struct rtl8169_private *tp)
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@ -1184,7 +1164,7 @@ static void rtl8168ep_driver_start(struct rtl8169_private *tp)
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r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
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r8168ep_ocp_write(tp, 0x01, 0x30,
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r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
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rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
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rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
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}
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static void rtl8168_driver_start(struct rtl8169_private *tp)
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@ -1207,7 +1187,7 @@ static void rtl8168_driver_start(struct rtl8169_private *tp)
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static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
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{
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r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
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rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
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rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
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}
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static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
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@ -1216,7 +1196,7 @@ static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
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r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
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r8168ep_ocp_write(tp, 0x01, 0x30,
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r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
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rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
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rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
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}
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static void rtl8168_driver_stop(struct rtl8169_private *tp)
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@ -1277,7 +1257,7 @@ u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
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{
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RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
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return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
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return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
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RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
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}
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@ -1614,7 +1594,7 @@ static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
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RTL_W32(tp, CounterAddrLow, cmd);
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RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
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rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
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rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
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}
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static void rtl8169_reset_counters(struct rtl8169_private *tp)
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@ -2471,7 +2451,7 @@ static void rtl_hw_reset(struct rtl8169_private *tp)
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{
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RTL_W8(tp, ChipCmd, CmdReset);
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rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
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rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
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}
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static void rtl_request_firmware(struct rtl8169_private *tp)
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@ -2525,12 +2505,12 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_27:
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case RTL_GIGA_MAC_VER_28:
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case RTL_GIGA_MAC_VER_31:
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rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
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rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
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break;
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case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
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case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
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RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
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rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
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rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
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break;
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default:
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RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
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@ -2640,7 +2620,7 @@ static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
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RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
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CSIAR_BYTE_ENABLE | func << 16);
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rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
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rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
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}
|
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|
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static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
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@ -2650,7 +2630,7 @@ static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
|
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RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
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CSIAR_BYTE_ENABLE);
|
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|
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return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
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return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
|
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RTL_R32(tp, CSIDR) : ~0;
|
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}
|
||||
|
||||
@ -3605,7 +3585,7 @@ static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
|
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|
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r8168_mac_ocp_write(tp, 0xe098, 0xc302);
|
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|
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rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
|
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rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
|
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|
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rtl8125_config_eee_mac(tp);
|
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|
||||
@ -5148,10 +5128,10 @@ static void rtl_hw_init_8168g(struct rtl8169_private *tp)
|
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{
|
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RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
|
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|
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if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
|
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if (!rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
|
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return;
|
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|
||||
if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
|
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if (!rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
|
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return;
|
||||
|
||||
RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
|
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@ -5160,19 +5140,19 @@ static void rtl_hw_init_8168g(struct rtl8169_private *tp)
|
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|
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r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
|
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|
||||
if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
|
||||
if (!rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
|
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return;
|
||||
|
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r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
|
||||
|
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rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
|
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rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
|
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}
|
||||
|
||||
static void rtl_hw_init_8125(struct rtl8169_private *tp)
|
||||
{
|
||||
RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
|
||||
|
||||
if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
|
||||
if (!rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
|
||||
return;
|
||||
|
||||
RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
|
||||
@ -5181,14 +5161,14 @@ static void rtl_hw_init_8125(struct rtl8169_private *tp)
|
||||
|
||||
r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
|
||||
|
||||
if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
|
||||
if (!rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
|
||||
return;
|
||||
|
||||
r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
|
||||
r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
|
||||
r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
|
||||
|
||||
rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
|
||||
rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
|
||||
}
|
||||
|
||||
static void rtl_hw_initialize(struct rtl8169_private *tp)
|
||||
|
||||
@ -65,4 +65,15 @@ static inline void ssleep(unsigned int seconds)
|
||||
msleep(seconds * 1000);
|
||||
}
|
||||
|
||||
/* see Documentation/timers/timers-howto.rst for the thresholds */
|
||||
static inline void fsleep(unsigned long usecs)
|
||||
{
|
||||
if (usecs <= 10)
|
||||
udelay(usecs);
|
||||
else if (usecs <= 20000)
|
||||
usleep_range(usecs, 2 * usecs);
|
||||
else
|
||||
msleep(DIV_ROUND_UP(usecs, 1000));
|
||||
}
|
||||
|
||||
#endif /* defined(_LINUX_DELAY_H) */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user