AuxXxilium/linux_dsm_epyc7002
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ARM: dts: imx7d: Add node for PCIe controller

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Cc: yurovsky@gmail.com
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Andrey Smirnov 2017-05-15 07:53:04 -07:00 committed by Shawn Guo
parent 184f39b57c
commit a816d5750e
1 changed files with 37 additions and 0 deletions
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37
arch/arm/boot/dts/imx7d.dtsi
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@ -42,6 +42,7 @@
*/ */
#include "imx7s.dtsi" #include "imx7s.dtsi"
#include <dt-bindings/reset/imx7-reset.h>
/ { / {
cpus { cpus {
@ -127,6 +128,42 @@ fec2: ethernet@30bf0000 {
fsl,num-rx-queues=<3>; fsl,num-rx-queues=<3>;
status = "disabled"; status = "disabled";
}; };
pcie: pcie@0x33800000 {
compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
reg = <0x33800000 0x4000>,
<0x4ff00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
num-lanes = <1>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
<&clks IMX7D_PCIE_PHY_ROOT_CLK>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
<&clks IMX7D_PCIE_PHY_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
fsl,max-link-speed = <2>;
power-domains = <&pgc_pcie_phy>;
resets = <&src IMX7_RESET_PCIEPHY>,
<&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
reset-names = "pciephy", "apps";
status = "disabled";
};
}; };
&ca_funnel_ports { &ca_funnel_ports {