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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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net: ethernet: ti: cpsw: introduce mac sl module api
The MAC SL submodule has a lot of common functions between many of TI SoCs AM335x/AM437x/DRA7(AM57xx), Keystone 2 66AK2HK/E/L/G and K3 AM654, but there are also differences especially in registers offsets and sets of supported functions. This patch introduces the MAC SL submodule API which is intended to provide a common way to access the MAC SL submodule and hide HW integrations details. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Grygorii Strashko
David S. Miller
parent
e6a8462491
commit
a71a18f24d
328
drivers/net/ethernet/ti/cpsw_sl.c
Normal file
328
drivers/net/ethernet/ti/cpsw_sl.c
Normal file
@ -0,0 +1,328 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/
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* Ethernet MAC Sliver (CPGMAC_SL)
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*
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* Copyright (C) 2019 Texas Instruments
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*
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include "cpsw_sl.h"
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#define CPSW_SL_REG_NOTUSED U16_MAX
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static const u16 cpsw_sl_reg_map_cpsw[] = {
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[CPSW_SL_IDVER] = 0x00,
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[CPSW_SL_MACCONTROL] = 0x04,
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[CPSW_SL_MACSTATUS] = 0x08,
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[CPSW_SL_SOFT_RESET] = 0x0c,
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[CPSW_SL_RX_MAXLEN] = 0x10,
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[CPSW_SL_BOFFTEST] = 0x14,
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[CPSW_SL_RX_PAUSE] = 0x18,
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[CPSW_SL_TX_PAUSE] = 0x1c,
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[CPSW_SL_EMCONTROL] = 0x20,
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[CPSW_SL_RX_PRI_MAP] = 0x24,
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[CPSW_SL_TX_GAP] = 0x28,
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};
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static const u16 cpsw_sl_reg_map_66ak2hk[] = {
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[CPSW_SL_IDVER] = 0x00,
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[CPSW_SL_MACCONTROL] = 0x04,
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[CPSW_SL_MACSTATUS] = 0x08,
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[CPSW_SL_SOFT_RESET] = 0x0c,
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[CPSW_SL_RX_MAXLEN] = 0x10,
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[CPSW_SL_BOFFTEST] = CPSW_SL_REG_NOTUSED,
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[CPSW_SL_RX_PAUSE] = 0x18,
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[CPSW_SL_TX_PAUSE] = 0x1c,
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[CPSW_SL_EMCONTROL] = 0x20,
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[CPSW_SL_RX_PRI_MAP] = 0x24,
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[CPSW_SL_TX_GAP] = CPSW_SL_REG_NOTUSED,
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};
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static const u16 cpsw_sl_reg_map_66ak2x_xgbe[] = {
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[CPSW_SL_IDVER] = 0x00,
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[CPSW_SL_MACCONTROL] = 0x04,
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[CPSW_SL_MACSTATUS] = 0x08,
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[CPSW_SL_SOFT_RESET] = 0x0c,
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[CPSW_SL_RX_MAXLEN] = 0x10,
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[CPSW_SL_BOFFTEST] = CPSW_SL_REG_NOTUSED,
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[CPSW_SL_RX_PAUSE] = 0x18,
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[CPSW_SL_TX_PAUSE] = 0x1c,
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[CPSW_SL_EMCONTROL] = 0x20,
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[CPSW_SL_RX_PRI_MAP] = CPSW_SL_REG_NOTUSED,
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[CPSW_SL_TX_GAP] = 0x28,
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};
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static const u16 cpsw_sl_reg_map_66ak2elg_am65[] = {
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[CPSW_SL_IDVER] = CPSW_SL_REG_NOTUSED,
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[CPSW_SL_MACCONTROL] = 0x00,
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[CPSW_SL_MACSTATUS] = 0x04,
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[CPSW_SL_SOFT_RESET] = 0x08,
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[CPSW_SL_RX_MAXLEN] = CPSW_SL_REG_NOTUSED,
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[CPSW_SL_BOFFTEST] = 0x0c,
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[CPSW_SL_RX_PAUSE] = 0x10,
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[CPSW_SL_TX_PAUSE] = 0x40,
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[CPSW_SL_EMCONTROL] = 0x70,
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[CPSW_SL_RX_PRI_MAP] = CPSW_SL_REG_NOTUSED,
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[CPSW_SL_TX_GAP] = 0x74,
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};
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#define CPSW_SL_SOFT_RESET_BIT BIT(0)
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#define CPSW_SL_STATUS_PN_IDLE BIT(31)
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#define CPSW_SL_AM65_STATUS_PN_E_IDLE BIT(30)
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#define CPSW_SL_AM65_STATUS_PN_P_IDLE BIT(29)
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#define CPSW_SL_AM65_STATUS_PN_TX_IDLE BIT(28)
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#define CPSW_SL_STATUS_IDLE_MASK_BASE (CPSW_SL_STATUS_PN_IDLE)
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#define CPSW_SL_STATUS_IDLE_MASK_K3 \
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(CPSW_SL_STATUS_IDLE_MASK_BASE | CPSW_SL_AM65_STATUS_PN_E_IDLE | \
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CPSW_SL_AM65_STATUS_PN_P_IDLE | CPSW_SL_AM65_STATUS_PN_TX_IDLE)
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#define CPSW_SL_CTL_FUNC_BASE \
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(CPSW_SL_CTL_FULLDUPLEX |\
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CPSW_SL_CTL_LOOPBACK |\
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CPSW_SL_CTL_RX_FLOW_EN |\
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CPSW_SL_CTL_TX_FLOW_EN |\
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CPSW_SL_CTL_GMII_EN |\
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CPSW_SL_CTL_TX_PACE |\
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CPSW_SL_CTL_GIG |\
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CPSW_SL_CTL_CMD_IDLE |\
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CPSW_SL_CTL_IFCTL_A |\
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CPSW_SL_CTL_IFCTL_B |\
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CPSW_SL_CTL_GIG_FORCE |\
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CPSW_SL_CTL_EXT_EN |\
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CPSW_SL_CTL_RX_CEF_EN |\
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CPSW_SL_CTL_RX_CSF_EN |\
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CPSW_SL_CTL_RX_CMF_EN)
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struct cpsw_sl {
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struct device *dev;
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void __iomem *sl_base;
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const u16 *regs;
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u32 control_features;
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u32 idle_mask;
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};
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struct cpsw_sl_dev_id {
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const char *device_id;
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const u16 *regs;
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const u32 control_features;
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const u32 regs_offset;
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const u32 idle_mask;
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};
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static const struct cpsw_sl_dev_id cpsw_sl_id_match[] = {
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{
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.device_id = "cpsw",
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.regs = cpsw_sl_reg_map_cpsw,
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.control_features = CPSW_SL_CTL_FUNC_BASE |
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CPSW_SL_CTL_MTEST |
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CPSW_SL_CTL_TX_SHORT_GAP_EN |
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CPSW_SL_CTL_TX_SG_LIM_EN,
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.idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE,
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},
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{
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.device_id = "66ak2hk",
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.regs = cpsw_sl_reg_map_66ak2hk,
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.control_features = CPSW_SL_CTL_FUNC_BASE |
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CPSW_SL_CTL_TX_SHORT_GAP_EN,
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.idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE,
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},
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{
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.device_id = "66ak2x_xgbe",
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.regs = cpsw_sl_reg_map_66ak2x_xgbe,
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.control_features = CPSW_SL_CTL_FUNC_BASE |
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CPSW_SL_CTL_XGIG |
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CPSW_SL_CTL_TX_SHORT_GAP_EN |
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CPSW_SL_CTL_CRC_TYPE |
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CPSW_SL_CTL_XGMII_EN,
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.idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE,
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},
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{
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.device_id = "66ak2el",
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.regs = cpsw_sl_reg_map_66ak2elg_am65,
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.regs_offset = 0x330,
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.control_features = CPSW_SL_CTL_FUNC_BASE |
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CPSW_SL_CTL_MTEST |
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CPSW_SL_CTL_TX_SHORT_GAP_EN |
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CPSW_SL_CTL_CRC_TYPE |
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CPSW_SL_CTL_EXT_EN_RX_FLO |
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CPSW_SL_CTL_EXT_EN_TX_FLO |
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CPSW_SL_CTL_TX_SG_LIM_EN,
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.idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE,
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},
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{
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.device_id = "66ak2g",
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.regs = cpsw_sl_reg_map_66ak2elg_am65,
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.regs_offset = 0x330,
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.control_features = CPSW_SL_CTL_FUNC_BASE |
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CPSW_SL_CTL_MTEST |
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CPSW_SL_CTL_CRC_TYPE |
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CPSW_SL_CTL_EXT_EN_RX_FLO |
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CPSW_SL_CTL_EXT_EN_TX_FLO,
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},
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{
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.device_id = "am65",
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.regs = cpsw_sl_reg_map_66ak2elg_am65,
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.regs_offset = 0x330,
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.control_features = CPSW_SL_CTL_FUNC_BASE |
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CPSW_SL_CTL_MTEST |
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CPSW_SL_CTL_XGIG |
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CPSW_SL_CTL_TX_SHORT_GAP_EN |
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CPSW_SL_CTL_CRC_TYPE |
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CPSW_SL_CTL_XGMII_EN |
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CPSW_SL_CTL_EXT_EN_RX_FLO |
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CPSW_SL_CTL_EXT_EN_TX_FLO |
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CPSW_SL_CTL_TX_SG_LIM_EN |
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CPSW_SL_CTL_EXT_EN_XGIG,
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.idle_mask = CPSW_SL_STATUS_IDLE_MASK_K3,
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},
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{ },
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};
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u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg)
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{
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int val;
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if (sl->regs[reg] == CPSW_SL_REG_NOTUSED) {
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dev_err(sl->dev, "cpsw_sl: not sup r reg: %04X\n",
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sl->regs[reg]);
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return 0;
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}
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val = readl(sl->sl_base + sl->regs[reg]);
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dev_dbg(sl->dev, "cpsw_sl: reg: %04X r 0x%08X\n", sl->regs[reg], val);
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return val;
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}
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void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val)
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{
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if (sl->regs[reg] == CPSW_SL_REG_NOTUSED) {
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dev_err(sl->dev, "cpsw_sl: not sup w reg: %04X\n",
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sl->regs[reg]);
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return;
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}
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dev_dbg(sl->dev, "cpsw_sl: reg: %04X w 0x%08X\n", sl->regs[reg], val);
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writel(val, sl->sl_base + sl->regs[reg]);
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}
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static const struct cpsw_sl_dev_id *cpsw_sl_match_id(
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const struct cpsw_sl_dev_id *id,
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const char *device_id)
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{
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if (!id || !device_id)
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return NULL;
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while (id->device_id) {
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if (strcmp(device_id, id->device_id) == 0)
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return id;
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id++;
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}
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return NULL;
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}
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struct cpsw_sl *cpsw_sl_get(const char *device_id, struct device *dev,
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void __iomem *sl_base)
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{
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const struct cpsw_sl_dev_id *sl_dev_id;
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struct cpsw_sl *sl;
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sl = devm_kzalloc(dev, sizeof(struct cpsw_sl), GFP_KERNEL);
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if (!sl)
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return ERR_PTR(-ENOMEM);
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sl->dev = dev;
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sl->sl_base = sl_base;
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sl_dev_id = cpsw_sl_match_id(cpsw_sl_id_match, device_id);
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if (!sl_dev_id) {
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dev_err(sl->dev, "cpsw_sl: dev_id %s not found.\n", device_id);
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return ERR_PTR(-EINVAL);
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}
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sl->regs = sl_dev_id->regs;
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sl->control_features = sl_dev_id->control_features;
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sl->idle_mask = sl_dev_id->idle_mask;
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sl->sl_base += sl_dev_id->regs_offset;
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return sl;
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}
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void cpsw_sl_reset(struct cpsw_sl *sl, unsigned long tmo)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(tmo);
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/* Set the soft reset bit */
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cpsw_sl_reg_write(sl, CPSW_SL_SOFT_RESET, CPSW_SL_SOFT_RESET_BIT);
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/* Wait for the bit to clear */
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do {
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usleep_range(100, 200);
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} while ((cpsw_sl_reg_read(sl, CPSW_SL_SOFT_RESET) &
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CPSW_SL_SOFT_RESET_BIT) &&
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time_after(timeout, jiffies));
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if (cpsw_sl_reg_read(sl, CPSW_SL_SOFT_RESET) & CPSW_SL_SOFT_RESET_BIT)
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dev_err(sl->dev, "cpsw_sl failed to soft-reset.\n");
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}
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u32 cpsw_sl_ctl_set(struct cpsw_sl *sl, u32 ctl_funcs)
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{
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u32 val;
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if (ctl_funcs & ~sl->control_features) {
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dev_err(sl->dev, "cpsw_sl: unsupported func 0x%08X\n",
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ctl_funcs & (~sl->control_features));
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return -EINVAL;
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}
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val = cpsw_sl_reg_read(sl, CPSW_SL_MACCONTROL);
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val |= ctl_funcs;
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cpsw_sl_reg_write(sl, CPSW_SL_MACCONTROL, val);
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return 0;
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}
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u32 cpsw_sl_ctl_clr(struct cpsw_sl *sl, u32 ctl_funcs)
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{
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u32 val;
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if (ctl_funcs & ~sl->control_features) {
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dev_err(sl->dev, "cpsw_sl: unsupported func 0x%08X\n",
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ctl_funcs & (~sl->control_features));
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return -EINVAL;
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}
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val = cpsw_sl_reg_read(sl, CPSW_SL_MACCONTROL);
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val &= ~ctl_funcs;
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cpsw_sl_reg_write(sl, CPSW_SL_MACCONTROL, val);
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return 0;
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}
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void cpsw_sl_ctl_reset(struct cpsw_sl *sl)
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{
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cpsw_sl_reg_write(sl, CPSW_SL_MACCONTROL, 0);
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}
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int cpsw_sl_wait_for_idle(struct cpsw_sl *sl, unsigned long tmo)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(tmo);
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do {
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usleep_range(100, 200);
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} while (!(cpsw_sl_reg_read(sl, CPSW_SL_MACSTATUS) &
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sl->idle_mask) && time_after(timeout, jiffies));
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if (!(cpsw_sl_reg_read(sl, CPSW_SL_MACSTATUS) & sl->idle_mask)) {
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dev_err(sl->dev, "cpsw_sl failed to soft-reset.\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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73
drivers/net/ethernet/ti/cpsw_sl.h
Normal file
73
drivers/net/ethernet/ti/cpsw_sl.h
Normal file
@ -0,0 +1,73 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/
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* Ethernet MAC Sliver (CPGMAC_SL) APIs
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*
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* Copyright (C) 2019 Texas Instruments
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*
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*/
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#ifndef __TI_CPSW_SL_H__
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#define __TI_CPSW_SL_H__
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#include <linux/device.h>
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enum cpsw_sl_regs {
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CPSW_SL_IDVER,
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CPSW_SL_MACCONTROL,
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CPSW_SL_MACSTATUS,
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CPSW_SL_SOFT_RESET,
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CPSW_SL_RX_MAXLEN,
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CPSW_SL_BOFFTEST,
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CPSW_SL_RX_PAUSE,
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CPSW_SL_TX_PAUSE,
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CPSW_SL_EMCONTROL,
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CPSW_SL_RX_PRI_MAP,
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CPSW_SL_TX_GAP,
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};
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enum {
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CPSW_SL_CTL_FULLDUPLEX = BIT(0), /* Full Duplex mode */
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CPSW_SL_CTL_LOOPBACK = BIT(1), /* Loop Back Mode */
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CPSW_SL_CTL_MTEST = BIT(2), /* Manufacturing Test mode */
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CPSW_SL_CTL_RX_FLOW_EN = BIT(3), /* Receive Flow Control Enable */
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CPSW_SL_CTL_TX_FLOW_EN = BIT(4), /* Transmit Flow Control Enable */
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CPSW_SL_CTL_GMII_EN = BIT(5), /* GMII Enable */
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CPSW_SL_CTL_TX_PACE = BIT(6), /* Transmit Pacing Enable */
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CPSW_SL_CTL_GIG = BIT(7), /* Gigabit Mode */
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CPSW_SL_CTL_XGIG = BIT(8), /* 10 Gigabit Mode */
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CPSW_SL_CTL_TX_SHORT_GAP_EN = BIT(10), /* Transmit Short Gap Enable */
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CPSW_SL_CTL_CMD_IDLE = BIT(11), /* Command Idle */
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CPSW_SL_CTL_CRC_TYPE = BIT(12), /* Port CRC Type */
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CPSW_SL_CTL_XGMII_EN = BIT(13), /* XGMII Enable */
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CPSW_SL_CTL_IFCTL_A = BIT(15), /* Interface Control A */
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CPSW_SL_CTL_IFCTL_B = BIT(16), /* Interface Control B */
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CPSW_SL_CTL_GIG_FORCE = BIT(17), /* Gigabit Mode Force */
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CPSW_SL_CTL_EXT_EN = BIT(18), /* External Control Enable */
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CPSW_SL_CTL_EXT_EN_RX_FLO = BIT(19), /* Ext RX Flow Control Enable */
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CPSW_SL_CTL_EXT_EN_TX_FLO = BIT(20), /* Ext TX Flow Control Enable */
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CPSW_SL_CTL_TX_SG_LIM_EN = BIT(21), /* TXt Short Gap Limit Enable */
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CPSW_SL_CTL_RX_CEF_EN = BIT(22), /* RX Copy Error Frames Enable */
|
||||
CPSW_SL_CTL_RX_CSF_EN = BIT(23), /* RX Copy Short Frames Enable */
|
||||
CPSW_SL_CTL_RX_CMF_EN = BIT(24), /* RX Copy MAC Control Frames Enable */
|
||||
CPSW_SL_CTL_EXT_EN_XGIG = BIT(25), /* Ext XGIG Control En, k3 only */
|
||||
|
||||
CPSW_SL_CTL_FUNCS_COUNT
|
||||
};
|
||||
|
||||
struct cpsw_sl;
|
||||
|
||||
struct cpsw_sl *cpsw_sl_get(const char *device_id, struct device *dev,
|
||||
void __iomem *sl_base);
|
||||
|
||||
void cpsw_sl_reset(struct cpsw_sl *sl, unsigned long tmo);
|
||||
|
||||
u32 cpsw_sl_ctl_set(struct cpsw_sl *sl, u32 ctl_funcs);
|
||||
u32 cpsw_sl_ctl_clr(struct cpsw_sl *sl, u32 ctl_funcs);
|
||||
void cpsw_sl_ctl_reset(struct cpsw_sl *sl);
|
||||
int cpsw_sl_wait_for_idle(struct cpsw_sl *sl, unsigned long tmo);
|
||||
|
||||
u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg);
|
||||
void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val);
|
||||
|
||||
#endif /* __TI_CPSW_SL_H__ */
|
||||
Loading…
Reference in New Issue
Block a user