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MIPS: Octeon: Add register definitions for MGMT Ethernet driver.
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
parent
24479d9f46
commit
a7187a2ffc
1194
arch/mips/include/asm/octeon/cvmx-agl-defs.h
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1194
arch/mips/include/asm/octeon/cvmx-agl-defs.h
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File diff suppressed because it is too large
Load Diff
248
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
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248
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
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/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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#ifndef __CVMX_MIXX_DEFS_H__
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#define __CVMX_MIXX_DEFS_H__
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#define CVMX_MIXX_BIST(offset) \
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CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048))
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#define CVMX_MIXX_CTL(offset) \
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CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048))
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#define CVMX_MIXX_INTENA(offset) \
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CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048))
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#define CVMX_MIXX_IRCNT(offset) \
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CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048))
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#define CVMX_MIXX_IRHWM(offset) \
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CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048))
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#define CVMX_MIXX_IRING1(offset) \
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CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048))
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#define CVMX_MIXX_IRING2(offset) \
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CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048))
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#define CVMX_MIXX_ISR(offset) \
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CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
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#define CVMX_MIXX_ORCNT(offset) \
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CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
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#define CVMX_MIXX_ORHWM(offset) \
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CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
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#define CVMX_MIXX_ORING1(offset) \
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CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
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#define CVMX_MIXX_ORING2(offset) \
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CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
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#define CVMX_MIXX_REMCNT(offset) \
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CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
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union cvmx_mixx_bist {
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uint64_t u64;
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struct cvmx_mixx_bist_s {
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uint64_t reserved_4_63:60;
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uint64_t mrqdat:1;
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uint64_t ipfdat:1;
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uint64_t irfdat:1;
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uint64_t orfdat:1;
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} s;
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struct cvmx_mixx_bist_s cn52xx;
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struct cvmx_mixx_bist_s cn52xxp1;
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struct cvmx_mixx_bist_s cn56xx;
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struct cvmx_mixx_bist_s cn56xxp1;
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};
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union cvmx_mixx_ctl {
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uint64_t u64;
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struct cvmx_mixx_ctl_s {
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uint64_t reserved_8_63:56;
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uint64_t crc_strip:1;
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uint64_t busy:1;
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uint64_t en:1;
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uint64_t reset:1;
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uint64_t lendian:1;
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uint64_t nbtarb:1;
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uint64_t mrq_hwm:2;
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} s;
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struct cvmx_mixx_ctl_s cn52xx;
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struct cvmx_mixx_ctl_s cn52xxp1;
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struct cvmx_mixx_ctl_s cn56xx;
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struct cvmx_mixx_ctl_s cn56xxp1;
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};
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union cvmx_mixx_intena {
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uint64_t u64;
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struct cvmx_mixx_intena_s {
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uint64_t reserved_7_63:57;
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uint64_t orunena:1;
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uint64_t irunena:1;
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uint64_t data_drpena:1;
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uint64_t ithena:1;
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uint64_t othena:1;
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uint64_t ivfena:1;
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uint64_t ovfena:1;
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} s;
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struct cvmx_mixx_intena_s cn52xx;
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struct cvmx_mixx_intena_s cn52xxp1;
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struct cvmx_mixx_intena_s cn56xx;
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struct cvmx_mixx_intena_s cn56xxp1;
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};
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union cvmx_mixx_ircnt {
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uint64_t u64;
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struct cvmx_mixx_ircnt_s {
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uint64_t reserved_20_63:44;
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uint64_t ircnt:20;
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} s;
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struct cvmx_mixx_ircnt_s cn52xx;
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struct cvmx_mixx_ircnt_s cn52xxp1;
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struct cvmx_mixx_ircnt_s cn56xx;
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struct cvmx_mixx_ircnt_s cn56xxp1;
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};
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union cvmx_mixx_irhwm {
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uint64_t u64;
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struct cvmx_mixx_irhwm_s {
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uint64_t reserved_40_63:24;
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uint64_t ibplwm:20;
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uint64_t irhwm:20;
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} s;
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struct cvmx_mixx_irhwm_s cn52xx;
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struct cvmx_mixx_irhwm_s cn52xxp1;
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struct cvmx_mixx_irhwm_s cn56xx;
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struct cvmx_mixx_irhwm_s cn56xxp1;
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};
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union cvmx_mixx_iring1 {
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uint64_t u64;
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struct cvmx_mixx_iring1_s {
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uint64_t reserved_60_63:4;
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uint64_t isize:20;
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uint64_t reserved_36_39:4;
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uint64_t ibase:33;
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uint64_t reserved_0_2:3;
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} s;
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struct cvmx_mixx_iring1_s cn52xx;
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struct cvmx_mixx_iring1_s cn52xxp1;
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struct cvmx_mixx_iring1_s cn56xx;
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struct cvmx_mixx_iring1_s cn56xxp1;
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};
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union cvmx_mixx_iring2 {
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uint64_t u64;
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struct cvmx_mixx_iring2_s {
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uint64_t reserved_52_63:12;
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uint64_t itlptr:20;
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uint64_t reserved_20_31:12;
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uint64_t idbell:20;
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} s;
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struct cvmx_mixx_iring2_s cn52xx;
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struct cvmx_mixx_iring2_s cn52xxp1;
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struct cvmx_mixx_iring2_s cn56xx;
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struct cvmx_mixx_iring2_s cn56xxp1;
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};
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union cvmx_mixx_isr {
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uint64_t u64;
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struct cvmx_mixx_isr_s {
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uint64_t reserved_7_63:57;
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uint64_t orun:1;
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uint64_t irun:1;
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uint64_t data_drp:1;
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uint64_t irthresh:1;
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uint64_t orthresh:1;
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uint64_t idblovf:1;
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uint64_t odblovf:1;
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} s;
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struct cvmx_mixx_isr_s cn52xx;
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struct cvmx_mixx_isr_s cn52xxp1;
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struct cvmx_mixx_isr_s cn56xx;
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struct cvmx_mixx_isr_s cn56xxp1;
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};
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union cvmx_mixx_orcnt {
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uint64_t u64;
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struct cvmx_mixx_orcnt_s {
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uint64_t reserved_20_63:44;
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uint64_t orcnt:20;
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} s;
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struct cvmx_mixx_orcnt_s cn52xx;
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struct cvmx_mixx_orcnt_s cn52xxp1;
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struct cvmx_mixx_orcnt_s cn56xx;
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struct cvmx_mixx_orcnt_s cn56xxp1;
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};
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union cvmx_mixx_orhwm {
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uint64_t u64;
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struct cvmx_mixx_orhwm_s {
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uint64_t reserved_20_63:44;
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uint64_t orhwm:20;
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} s;
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struct cvmx_mixx_orhwm_s cn52xx;
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struct cvmx_mixx_orhwm_s cn52xxp1;
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struct cvmx_mixx_orhwm_s cn56xx;
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struct cvmx_mixx_orhwm_s cn56xxp1;
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};
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union cvmx_mixx_oring1 {
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uint64_t u64;
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struct cvmx_mixx_oring1_s {
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uint64_t reserved_60_63:4;
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uint64_t osize:20;
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uint64_t reserved_36_39:4;
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uint64_t obase:33;
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uint64_t reserved_0_2:3;
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} s;
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struct cvmx_mixx_oring1_s cn52xx;
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struct cvmx_mixx_oring1_s cn52xxp1;
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struct cvmx_mixx_oring1_s cn56xx;
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struct cvmx_mixx_oring1_s cn56xxp1;
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};
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union cvmx_mixx_oring2 {
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uint64_t u64;
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struct cvmx_mixx_oring2_s {
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uint64_t reserved_52_63:12;
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uint64_t otlptr:20;
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uint64_t reserved_20_31:12;
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uint64_t odbell:20;
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} s;
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struct cvmx_mixx_oring2_s cn52xx;
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struct cvmx_mixx_oring2_s cn52xxp1;
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struct cvmx_mixx_oring2_s cn56xx;
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struct cvmx_mixx_oring2_s cn56xxp1;
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};
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union cvmx_mixx_remcnt {
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uint64_t u64;
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struct cvmx_mixx_remcnt_s {
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uint64_t reserved_52_63:12;
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uint64_t iremcnt:20;
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uint64_t reserved_20_31:12;
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uint64_t oremcnt:20;
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} s;
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struct cvmx_mixx_remcnt_s cn52xx;
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struct cvmx_mixx_remcnt_s cn52xxp1;
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struct cvmx_mixx_remcnt_s cn56xx;
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struct cvmx_mixx_remcnt_s cn56xxp1;
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};
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#endif
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