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drm/mgag200: Move mode-setting code into separate helper function
The mode-setting code is now located in mgag200_set_mode_regs(), sans a few flags that will be moved in a later patch for clarity. v2: * replace uint8_t with u8 Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Tested-by: John Donnelly <John.p.donnelly@oracle.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Acked-by: Emil Velikov <emil.velikov@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200515083233.32036-5-tzimmermann@suse.de
This commit is contained in:
Thomas Zimmermann
parent
fb724f1e4b
commit
a6edae07fd
@ -911,6 +911,79 @@ static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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return mga_crtc_do_set_base(mdev, fb, old_fb);
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}
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static void mgag200_set_mode_regs(struct mga_device *mdev,
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const struct drm_display_mode *mode)
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{
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unsigned int hdisplay, hsyncstart, hsyncend, htotal;
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unsigned int vdisplay, vsyncstart, vsyncend, vtotal;
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u8 misc = 0;
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u8 crtcext1, crtcext2, crtcext5;
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hdisplay = mode->hdisplay / 8 - 1;
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hsyncstart = mode->hsync_start / 8 - 1;
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hsyncend = mode->hsync_end / 8 - 1;
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htotal = mode->htotal / 8 - 1;
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/* Work around hardware quirk */
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if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
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htotal++;
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vdisplay = mode->vdisplay - 1;
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vsyncstart = mode->vsync_start - 1;
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vsyncend = mode->vsync_end - 1;
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vtotal = mode->vtotal - 2;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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misc |= 0x40;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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misc |= 0x80;
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crtcext1 = (((htotal - 4) & 0x100) >> 8) |
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((hdisplay & 0x100) >> 7) |
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((hsyncstart & 0x100) >> 6) |
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(htotal & 0x40);
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if (mdev->type == G200_WB || mdev->type == G200_EW3)
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crtcext1 |= BIT(7) | /* vrsten */
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BIT(3); /* hrsten */
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crtcext2 = ((vtotal & 0xc00) >> 10) |
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((vdisplay & 0x400) >> 8) |
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((vdisplay & 0xc00) >> 7) |
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((vsyncstart & 0xc00) >> 5) |
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((vdisplay & 0x400) >> 3);
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crtcext5 = 0x00;
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WREG_CRT(0, htotal - 4);
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WREG_CRT(1, hdisplay);
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WREG_CRT(2, hdisplay);
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WREG_CRT(3, (htotal & 0x1F) | 0x80);
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WREG_CRT(4, hsyncstart);
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WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
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WREG_CRT(6, vtotal & 0xFF);
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WREG_CRT(7, ((vtotal & 0x100) >> 8) |
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((vdisplay & 0x100) >> 7) |
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((vsyncstart & 0x100) >> 6) |
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((vdisplay & 0x100) >> 5) |
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((vdisplay & 0x100) >> 4) | /* linecomp */
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((vtotal & 0x200) >> 4) |
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((vdisplay & 0x200) >> 3) |
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((vsyncstart & 0x200) >> 2));
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WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
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((vdisplay & 0x200) >> 3));
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WREG_CRT(16, vsyncstart & 0xFF);
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WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
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WREG_CRT(18, vdisplay & 0xFF);
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WREG_CRT(20, 0);
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WREG_CRT(21, vdisplay & 0xFF);
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WREG_CRT(22, (vtotal + 1) & 0xFF);
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WREG_CRT(23, 0xc3);
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WREG_CRT(24, vdisplay & 0xFF);
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WREG_ECRT(0x01, crtcext1);
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WREG_ECRT(0x02, crtcext2);
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WREG_ECRT(0x05, crtcext5);
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}
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static int mga_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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@ -919,8 +992,6 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_device *dev = crtc->dev;
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struct mga_device *mdev = to_mga_device(dev);
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const struct drm_framebuffer *fb = crtc->primary->fb;
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int hdisplay, hsyncstart, hsyncend, htotal;
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int vdisplay, vsyncstart, vsyncend, vtotal;
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int pitch;
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int option = 0, option2 = 0;
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int i;
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@ -999,12 +1070,6 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
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break;
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}
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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misc |= 0x40;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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misc |= 0x80;
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for (i = 0; i < sizeof(dacvalue); i++) {
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if ((i <= 0x17) ||
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(i == 0x1b) ||
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@ -1044,20 +1109,6 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
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else
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pitch = pitch >> (4 - bppshift);
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hdisplay = mode->hdisplay / 8 - 1;
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hsyncstart = mode->hsync_start / 8 - 1;
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hsyncend = mode->hsync_end / 8 - 1;
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htotal = mode->htotal / 8 - 1;
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/* Work around hardware quirk */
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if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
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htotal++;
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vdisplay = mode->vdisplay - 1;
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vsyncstart = mode->vsync_start - 1;
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vsyncend = mode->vsync_end - 1;
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vtotal = mode->vtotal - 2;
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WREG_GFX(0, 0);
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WREG_GFX(1, 0);
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WREG_GFX(2, 0);
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@ -1068,61 +1119,26 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
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WREG_GFX(7, 0xf);
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WREG_GFX(8, 0xf);
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WREG_CRT(0, htotal - 4);
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WREG_CRT(1, hdisplay);
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WREG_CRT(2, hdisplay);
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WREG_CRT(3, (htotal & 0x1F) | 0x80);
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WREG_CRT(4, hsyncstart);
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WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
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WREG_CRT(6, vtotal & 0xFF);
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WREG_CRT(7, ((vtotal & 0x100) >> 8) |
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((vdisplay & 0x100) >> 7) |
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((vsyncstart & 0x100) >> 6) |
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((vdisplay & 0x100) >> 5) |
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((vdisplay & 0x100) >> 4) | /* linecomp */
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((vtotal & 0x200) >> 4)|
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((vdisplay & 0x200) >> 3) |
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((vsyncstart & 0x200) >> 2));
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WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
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((vdisplay & 0x200) >> 3));
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WREG_CRT(10, 0);
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WREG_CRT(11, 0);
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WREG_CRT(12, 0);
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WREG_CRT(13, 0);
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WREG_CRT(14, 0);
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WREG_CRT(15, 0);
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WREG_CRT(16, vsyncstart & 0xFF);
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WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
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WREG_CRT(18, vdisplay & 0xFF);
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WREG_CRT(19, pitch & 0xFF);
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WREG_CRT(20, 0);
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WREG_CRT(21, vdisplay & 0xFF);
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WREG_CRT(22, (vtotal + 1) & 0xFF);
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WREG_CRT(23, 0xc3);
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WREG_CRT(24, vdisplay & 0xFF);
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mgag200_set_mode_regs(mdev, mode);
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ext_vga[0] = 0;
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ext_vga[5] = 0;
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/* TODO interlace */
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ext_vga[0] |= (pitch & 0x300) >> 4;
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ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
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((hdisplay & 0x100) >> 7) |
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((hsyncstart & 0x100) >> 6) |
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(htotal & 0x40);
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ext_vga[2] = ((vtotal & 0xc00) >> 10) |
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((vdisplay & 0x400) >> 8) |
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((vdisplay & 0xc00) >> 7) |
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((vsyncstart & 0xc00) >> 5) |
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((vdisplay & 0x400) >> 3);
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if (fb->format->cpp[0] * 8 == 24)
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ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
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else
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ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
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ext_vga[4] = 0;
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if (mdev->type == G200_WB || mdev->type == G200_EW3)
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ext_vga[1] |= 0x88;
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/* Set pixel clocks */
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misc = 0x2d;
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@ -1130,9 +1146,9 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
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mga_crtc_set_plls(mdev, mode->clock);
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for (i = 0; i < 6; i++) {
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WREG_ECRT(i, ext_vga[i]);
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}
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WREG_ECRT(0, ext_vga[0]);
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WREG_ECRT(3, ext_vga[3]);
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WREG_ECRT(4, ext_vga[4]);
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if (mdev->type == G200_ER)
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WREG_ECRT(0x24, 0x5);
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